Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain

Abstract

Structural modifications of 5-nm node nanosheet FETs (NSFETs) were quantitatively analyzed using fully calibrated TCAD. The NSFETs with crescent inner spacer improve the short-channel effects by increasing effective gate lengths but also increase the parasitic capacitances by greater outer fringing electric field. The NSFETs with a crescent inner spacer and slanted source/drain (S/D) increase the physical gate lengths of bottom NS channel, but the anisotropic over-etching of substrate regions induces punchthrough effect at the bottom transistor. Bottom isolation by depositing dielectrics prior to S/D formation is effective to eliminate the punchthrough effect as well as to attain shorter RC delay by better electrostatics and parasitic capacitance reduction. In addition, the isolated S/D NSFETs without punchthrough stopper decrease parasitic and gate capacitances further at the frequency greater than 600 MHz at which the inversion carriers are not formed at the bottom transistor. Thus, although the crescent inner spacer and slanted S/D structure are unintendedly formed under process, these modifications lead to the performance boosting and the process simplicity of the 5-nm node NSFETs.