Punch-through Effect Research Articles

Stacked gate mid-channel injection flash EEPROM cell. I. Programming speed and efficiency versus device structure

Presents a new flash EEPROM cell which has been fabricated to achieve fast programming with low power. This memory cell attains speed and efficiency, comparable to the split-gate device, while preserving a simple stacked gate structure. The device programs faster than the stacked gate cell by a factor of about ten. Also, the threshold voltage shift of 5 V can be accomplished with the drain voltage of 3 V in about 50 /spl mu/s. The proposed memory cell is strongly resistant against the punchthrough effect and is capable of erasure in byte unit at the drain side. Factors pertinent to programming are discussed, theoretically and experimentally, in correlation with device structures. The hot electron dwell time in the channel is shown to be an important parameter, affecting the programming speed and efficiency.

Vertical Si p-MOS transistor selectively grown by low pressure chemical vapour deposition

Low pressure chemical vapour deposition was used to define the channel length of vertical Si p-MOS transistors. Comparing to a conventional lateral transistor, the vertical structure is expected to enhance the packing density. The growth technique permits an easy reduction of the channel length without complex technological preparation steps. Besides, it allows a selective deposition in which facet growth occurs, which in turn leads to a thinner channel length compared to the distance between the two pn-junctions in the volume area. Therefore, the facet growth leads to a shift of the punch-through effect to higher voltages. Device characteristics of a non-optimized transistor geometry, on which the gate oxide is prepared after the epitaxial growth, with a channel length of approximately 250 nm and a gate oxide thickness of 12 nm, show a transconductance of 70 mS mm −1, an ideal sub-threshold behaviour of 100 mV dec −1, an off-current below 10 −12 A μm −2 and a breakthrough voltage | V D|>4 V. Devices with a preparation of the gate oxide before epitaxial growth have also been studied. These devices show a transconductance of 25 mS mm −1 for a gate oxide thickness of 40 nm.

Reduction of parasitic bipolar transistor actionand punchthrough susceptibilityin MOSFETs using Si/Si 1-x Ge x sources and drains

Silicon CMOS devices are subject to some limitations as the dimensions are scaled down for VLSI applications. The incorporation of SiGe into the p-channel device can reduce parasitic bipolar action and punchthrough susceptibility. The authors compare the properties of elevated source and drain devices with and without Si/sub 1-x/Ge/sub x/ in the source and drain regions. We show that the parasitic bipolar gain is reduced by a factor of 18 and that the punchthrough effects seen in silicon devices are absent in the Si/sub 0.8/Ge/sub 0.2/ devices.

N/sup +/-polysilicon gate PMOSFET's with indium doped buried-channels

A n/sup +/-polysilicon gate PMOSFET with indium doped buried-channel is discussed, The gate length scaling of n/sup +/-polysilicon gate buried-length PMOSFET's is limited by the channel punch-through effect. Designing shallow counter-doped layers (buried-channels) has been established as a means to reduce the undesirable short channel effects in these devices. Indium, an acceptor dopant in Si, has a low diffusion coefficient and implant statistics favorable for achieving shallow doping layers. Indium implants are explored (as an alternative to BF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) to counter dope the n-tub for adjusting the threshold voltage. Devices are fabricated using AT&T's 0.5 μm CMOS technology but with t/sub ox/=50 /spl Aring/. Although no special effort has been made to optimize the n-tub or to take full advantage of the diffusion and implant characteristics of indium, excellent electrical results are obtained for devices with L/sub eff/=0.25 μm. Improved V/sub th/ roll-off characteristics and reduced body effect (/spl gamma//spl ap/0.18 V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> 2 / versus /spl gamma//sub B//spl ap/0.40 V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> 2 /) in indium implanted buried channels are demonstrated over BF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> implanted buried channels for PMOSFET's with identical long channel threshold voltages. The effects of incomplete ionization (freeze-out) of the indium acceptor states on the electrical device characteristics are demonstrated by device simulations and measurements.

Threshold voltage-minimum gate length trade-off in buried channel PMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> h) and the minimum gate length (L/sub m/in) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> h and L/sub m/in for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> h for a smaller L/sub m/in results in faster circuits for low supply voltage (3.3 to 1.8 V) n/sup +/-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> h for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> h (absolute value) is approximately 0.85-0.90 V.

Study of hot electron degradation in submicrometer gate length MOS transistor fabricated with selectively doped substrate engineering

Investigations are made on the performance and hot electron degradation of sub-μm MOS transistors fabricated with an improved selectively doped substrate (SDS) and with the conventional deep punch through implant (DPI) structures. The sub-μm gate length of the transistor was defined by a novel subtractive photolithography technique. The technique is described and the process details are given. The sub-μm transistor performance is characterised by electron mobility, inverse subthreshold slope, substrate sensitivity and drain induced barrier lowering (DIBL) for the two structures. The substrate current and hot electron degradation effect (HED) were measured and the results are compared for SDS and DPI techniques. It is shown that SDS structure reduces HED and surface punchthrough effects in sub-μm MOS transistors.

Detailed characterization and analysis of the breakdown voltage in fully depleted SOI n-MOSFET's

The breakdown voltage in fully depleted SOI n-MOSFET's has been studied over a wide range of film thicknesses, channel dopings, and channel lengths. In lightly-doped films, the breakdown voltage roll-off at shorter channel lengths becomes much less severe as the film thickness is reduced. This is a result of improved resistance to punchthrough and DIBL effects in thinner SOI. Consequently, at channel lengths below about 0.8 /spl mu/m, ultrathin (50 nm) SOI can provide better breakdown voltages than thicker films. At heavier doping levels the punchthrough and DIBL are suppressed, and there is little dependence of breakdown voltage on film thickness. Two-dimensional simulations have been used to investigate the breakdown behavior in these devices. It is found that the drain-induced barrier lowering affects the breakdown voltage both directly, via punchthrough, and indirectly through its effect on the current flow and hole generation in the high-field regions. >

Fabrication of a nanoscale, in-plane gated quantum wire by low energy ion exposure

The fabrication of a nanoscale gated quantum wire in a GaAs modulation doped field effect transistor substrate is described. Both the wire conduction channel, with a 110 nm physical width, and the gates were patterned into the two-dimensional electron gas of the substrate. This scheme produced in-plane gated devices with 110 nm gate lengths and 75 nm separations between the active areas. Electron-beam lithography was used to define masks for a subsequent flood exposure step with low energy argon ions (150 eV). This ion exposure technique produced very high gate-to-wire isolation, typically greater than 1014 Ω at 4.2 K. The in-plane design employed here drastically reduces gate capacitance compared with metal top-gate designs, and promises ultrafast switching times. These devices showed no short channel punch-through effects, exhibited low gate leakage, and had sufficient gain to permit integration of several such devices into more complex circuits such as logic gates.

Recovery of submicrometre p MOSFETs from hot carrier degradation by high field injection

Charge carrier tunnelling into gate oxide under high field strength (e.g. 8 MV/cm) is found to be an efficient method for the recovery of hot electron induced pMOSFET degradation, including hot electron induced punchthrough effects. The physical processes responsible for the recovery are investigated.

Shallow junctions, silicide requirements and process technologies for sub 0.5 μm CMOS

CMOS technology scaling dictates the reduction of the Source/Drain (S/D) junction depths to reduce punch-through and short channel effects. But simultaneously, lower contact resistances are needed as the device channel resistance decreases low S/D junction sheet resistance is required for improved density, and low S/D junction leakage should be maintained for reduced stand-by power and longer refresh time. In this paper, these conflicting requirements and several key technology elements for shallow junctions including silicide with thin TiSi 2 and the application of rapid thermal processing (RTP) will be presented. 0.25 μm CMOS S/D with junctions depths in the range of 0.1μm-0.15μm and less than 10 Ω□sheet resistance, exhibiting low leakage and contact resistance are demonstrated.

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 mu m is improved for the range of L 1.2 mu m, but is worse for L between 0.6 and 1.2 mu m. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V/sub TH/ as required for room-temperature operation are briefly discussed. >

Process limitation and device design tradeoffs of self-aligned TiSi/sub 2/ junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF/sub 2/, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi/sub 2/ p/sup +//n and n/sup +//p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi/sub 2/ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n/sup +//p and p/sup +//n junctions with junction depths of 0.12 to 0.20 mu m below the TiSi/sub 2/. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 mu m can be fabricated with such junctions. >

The dependence of drain-induced barrier lowering on substrate biasing in short channel PMOS devices at 77 K

This paper presents detailed experimental results on the substrate biasing characteristics of drain-induced barrier lowering DIBL at 77 K in short channel PMOS devices with boron ion channel doping. It was found that as the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias, and thereafter began decreasing. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, that includes device modeling at cryogenic temperatures, was used to investigate this unique feature of DIBL vs substrate biasing. From the simulation results, the dependence of DIBL on substrate biasing could be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, a new empirical model for describing this substrate bias-dependent characteristics of DIBL: (R) = δV TH (DIBL) δV DS = αL −β , α = α 0 + α 1 V BS, β = β 0 + β 1 V BS has been developed, and using this model, quantitative comparisons between 77 and 300 K results were made. These comparisons clearly show the improvement of DIBL at 77 K, especially for shorter channel devices. The experimental results could be explained physically by the transition of the subsurface current flow towards the surface current flow due to higher surface potential bending at 77 K. Further analysis were carried out with the emphasis on the variation of the threshold voltage definition and the boron ion channel doping profile. It was found that the extracted parameters α and β were very sensitive to the channel implant dose and energy, but were only slightly related to the threshold voltage definition.

Substrate bias effects on drain-induced barrier lowering in short-channel PMOS devices

It was found that, as the channel length decreased, the threshold voltage shift caused by drain-induced barrier lowering (DIBL) first increased with increasing substrate bias and then decreased as the channel length decreased further. The channel length (L/sub INT/) corresponding to an almost zero change of the DIBL variation with substrate bias was found to be between 0.78 and 0.90 mu m for the PMOS devices. This change in DIBL with substrate bias for devices with varying L can be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, an empirical model for describing this substrate bias characteristic of the DIBL effect is developed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Punch-through currents and floating strip potentials in silicon detectors

Punch-through currents flowing between adjacent p/sup +/ strips on the surface of silicon microstrip drift detectors have been observed. Measurements of the floating strip potential have shown that a p/sup +/ strip acquires a voltage such that the punch-through current and the leakage current are equal and opposite. The factors influencing the threshold for the punch-through effect have been compared with a simple computer model, and the predicted variation with the interstrip gap is found to be in reasonable agreement with measured values for a variety of detectors. >

Simulation of Josephson junction in a microwave field

The resistively shunted junction (RSJ) model of a Josephson junction in a microwave field is studied using both analog and digital simulators. A comparison of the two methods shows very good agreement. Voltage-current characteristics of the Josephson junction in the low-frequency limit and their transition to chaotic behavior due to the punchthrough effect are investigated. The inverse ac effect on high-β c junctions is simulated. Fractional inverse steps are found.

Electromagnetic-shower development in concrete and the punchthrough effect.

Electromagnetic-shower development in concrete and the punchthrough effect.

Hot-electron-induced punchthrough (HEIP) effect in submicrometer PMOSFET's

Degradation of device characterisitics due to hot-carrier injection in submicrometer PMOSFET has been investigated. We found that in submicrometer p-channel transistors the punchthrough voltage is seriously reduced due to hot-electon-induced punchthrough (HEIP). A worst case analysis of the experimental data shows substantially reduced lifetime due to HEIP.

Amorphous Silicon Alloy Punch-Through Diodes for Display Applications

AbstractThe current-voltage characteristics of amorphous silicon alloy n-π-n and p-i-p diodes have been investigated. These diodes show highly nonlinear conduction characteristics which are attributed to the punch-through effect. The dependence of the non-linearity on the thickness and doping of the intermediate active layer support this interpretation. An experimental 108 × 108 pixel liquid crystal display was built with punch-through diodes as pixel switches.

Design and fabrication of a GaAs vertical MESFET

Vertically oriented GaAs MESFET's were fabricated on thick epitaxial conductive layers grown by molecular-beam epitaxy on a semi-insulating substrate. The vertical channel pattern was defined by electron-beam lithography and included structures as small as 0.3- 0.4 µm on a total period of 1.0 µm. The vertical channels were formed by reactive ion etching, and the gate contact was formed by dual-angle evaporation. The top ohmic contacts were interconnected by a metal bridge supported by a dielectric layer. The drain characteristics displayed a drain punchthrough effect, indicating that a very short gate length was achieved. Microwave measurements indicated a maximum oscillation frequency of 12 GHz.