Pull-up Ratio Research Articles

Design and Analysis of XNOR-SRAM for In-Memory Computing

Abstract: The use of in-memory computing is a promising strategy with the potential to circumvent the von Neumann bottleneck and improve the overall performance of contemporary computer systems. In this study, the design and analysis of an innovative XNOR-SRAM cell for use in in-memory computing applications is presented. The performance of the suggested cell is assessed using crucial parameters such as cell ratio (CR), pull-up ratio (PR), static noise margin (SNM), write margin (WM), and read margin(RM)MA. Simulation and optimization of the proposed cell are carried out with the assistance of LTSPICE and the HSPICE tool . According to the findings, the XNOR-SRAM cell has greater performance when compared to the traditional 6T SRAM cell. This paves the way for the XNOR-SRAM cell to become a viable choice for in-memory computing.

Performance-Based Expressway Asphalt Pavement Structural Surface Layer Modulus Matching Mode Research

The current asphalt pavement design theory is a traditional line elastic theory. The voltage resistance recovery modulus is used as the material stiffness parameter in the design, which does not fully consider the significant differences between the road material pull-up modulus. Therefore, to improve the overall stress of the pavement structure, this article started from the perspective of the volume of the structure layer, analyzed the development characteristics of reflected cracks in terms of the modular volume of different surface layers, and studied the size of each layer. It is proposed to match the asphalt pavement layer modulus with the crack development level. Based on structural computing and simulation, the application of different modular matching modes was verified, and support was provided for the design of the pavement structure. The results showed that with the increase of the surface modulus, the stress intensity factor determined by a semi-analytical method showed a nonlinear decrease trend, and the change of stress intensity factor was not obvious when the modulus was greater than 10,000; the surface layer compression mode ratio increased, and the vertical deformation of the road surface and the top surface pressure of the road base slowly increased, especially when the volume of the pressure pull-up ratio was greater than 1.5. In addition, the impact of the constraint between the surface layer on the vertical deformation of the road table decreased with the decrease in the volume of the surface layer.

Accurate Estimation of Data Retention Voltage (DRV) for a 6T SRAM Cell at 45 nm, 65 nm, and 130 nm Technology Nodes

Scaling of supply voltage is one of the well-known methods for reducing leakage power. Data Retention Voltage (DRV) is the lower limit for the scaled voltage of SRAM. In this paper, we propose a modified analytical model for estimating the DRV of a 6T SRAM cell. The model is based on the sub-threshold current equations of the SRAM cell. The DRV of the 6T SRAM cell is computed using this model which is verified with the simulations carried out using the Cadence Virtuoso Tool. GPDK 45 nm, UMC 130 and 65 nm technology files are used for the validation of the model. The simulations are carried out for the 6T cell with different cell ratios and pull-up ratios. For each case, the DRV estimated from the model is nearly equal to the expected DRV calculated from simulations. The results matched well with the simulated results around 93%–79% whereas Qin’s model which matches only 75%–74%. This model shows better results than Qin’s model in terms of complexity and computation time. Furthermore, the proposed model is also validated for the calculation of DRV during process variation and shows better results.

A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks

We propose a novel ultra-low-power, voltage-based compute-in-memory (CIM) design with a new single-ended 8T SRAM bit cell structure. Since the proposed SRAM bit cell uses a single bitline for CIM calculation with decoupled read and write operations, it supports a much higher energy efficiency. In addition, to separate read and write operations, the stack structure of the read unit minimizes leakage power consumption. Moreover, the proposed bit cell structure provides better read and write stability due to the isolated read path, write path and greater pull-up ratio. Compared to the state-of-the-art SRAM-CIM, our proposed SRAM-CIM does not require extra transistors for CIM vector-matrix multiplication. We implemented a 16 k (128 × 128) bit cell array for the computation of 128× neurons, and used 64× binary inputs (0 or 1) and 64 × 128 binary weights (−1 or +1) values for the binary neural networks (BNNs). Each row of the bit cell array corresponding to a single neuron consists of a total of 128 cells, 64× cells for dot-product and 64× replicas cells for ADC reference. Additionally, 64× replica cells consist of 32× cells for ADC reference and 32× cells for offset calibration. We used a row-by-row ADC for the quantized outputs of each neuron, which supports 1–7 bits of output for each neuron. The ADC uses the sweeping method using 32× duplicate bit cells, and the sweep cycle is set to 2N−1+1, where N is the number of output bits. The simulation is performed at room temperature (27 °C) using 45 nm technology via Synopsys Hspice, and all transistors in bitcells use the minimum size considering the area, power, and speed. The proposed SRAM-CIM has reduced power consumption for vector-matrix multiplication by 99.96% compared to the existing state-of-the-art SRAM-CIM. Furthermore, because of the decoupled reading unit from an internal node of latch, there is no feedback from the reading unit, with read static noise, and margin-free results.

Optimisation of SRAM cell in 7-nm node by response surface method

ABSTRACT With CMOS process developing, the Static Random Access Memory (SRAM) suffers unavoidable degradation in terms of read and write stabilities. To optimise the memory with conventional 6-T cell in 7-nm process technology, Response Surface Method (RSM) is adopted to get the optimised relationship among the noise margin, the operating temperature, the supply voltage, the unit ratio, the pull-up ratio and the pre-charged voltage, et al. It shows that RSM approach is an effective statistical method for the optimisation of the SRAM cell, especially in the nano-scale scheme. In order to prove the superiority of the RSM approach, the noise margin variation is investigated from 90 nm to 7 nm technology nodes based on the general butterfly curves approach for the comparison. It shows that the stability of the SNM of the 6-T cell tends to be degraded with the continuous shrinkage of the process nodes. The RSM approach is demonstrated to be an effective way for the optimisation of the SRAM cell in single-digit nanometre node.

Performance evaluation of double gate tunnel FET based chain of inverters and 6-T SRAM cell

In this work, a Lookup table based verilog-A model is employed in cadence to evaluate the performance of the chain of inverters and 6-T SRAM cell based on double gate Tunnel-field-effect transistor (DGTFET). In order to drive large capacitance with fixed number of inverters stages with constant width of N type DGTFET (Wn), it is found that the time delay performance of the inverter chain depends on the ratio of width of P type DGTFET of nth stage (Wpn) to width of P type DGTFET of n-1th stage (Wpn−1). Simulation results investigated that the time delay is minimized to 0.265 ns for Wpn/Wpn−1 = 3. The impact of cell ratio (CR) and pull up ratio (PR) on the read stability and write ability of 6-T SRAM cell are investigated by using N curve simulations. It is observed that, increasing CR and PR strengthens the read stability and degrades the write ability of 6-T SRAM cell.

High Temperature Memory Design, Implementation, and Characterization in 1μm SiC CMOS Technology

Abstract Electronic systems capable of withstanding high temperature environments are in high demand in various applications such as logging-while-drilling (LWD) systems and embedded electronics which are in the core of gas turbine engine controls. Designing memory that can process massive amounts of data in harsh environments while consuming low power opens doors for next generation, smart, high temperature electronic systems. In this work, a CMOS based six transistor (6T) static random-access memory (SRAM) cell is designed and implemented in a state-of-the-art SiC 1μm triple well CMOS process. The designed SiC SRAM cell performance has been characterized for different values of cell ratios (CR) [0.5, 0.6, 1, 1.5, 2, 2.5] and pull-up ratios (PR) [1, 2, 3, 4, 5, 6] to determine the cell size with optimal performance parameters. Static noise margin (SNM) values for the different combinations of CR and PR are calculated using the model developed by Seevinck, et. al. [13]. The highest SNM values observed at 25°C and 300°C are 4.71 V and 4.65 V, respectively. Read static noise margin (RSNM) values of 1.94 V and 1.90 V are achieved at 25°C and 300°C, respectively. Analysis of measured data shows that the optimum cell size is with a CR of 2.5 and a PR of 6. However, these results are significantly impacted by highly resistive ohmic contacts.

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on area, power, performance and stability is analyzed showing that the most affected parameter is read stability, although this impact can be overcome using some of the read assist circuits proposed in the literature. The main benefits are layout regularity enhancement, with its consequent higher tolerance to variability, cell area reduction by 25 percent (with respect to a cell having a cell ratio of 2), leakage current improvement by a 35 percent, as well as energy dissipation reduction and a soft error rate per bit improvement of around 30 percent.

Ratios and distances of pull-up peaks observed in GlobalFiler kit data.

Short tandem repeat (STR) analysis is widely used for forensic examinations with a capillary electrophoresis instrument such as the 3500xL Genetic Analyzer. This instrument adapts multi-locus STR kits to examine up to 27 loci using a 6-fluorescent dye system and corrects the spectral overlap between each dye. However, inaccurate spectral correction can cause pull-up peaks. Here, we examined the pull-up peaks observed in GlobalFiler kit data in terms of their peak height ratios and distances from their parent allele peaks when using the 3500xL and the 3130xl Genetic Analyzers. With the 3500xL, 546 pull-up peaks were observed, and their pull-up ratios averaged 1.03 ± 0.32% (range 0.260-2.80%). Of the 546 pull-up peaks, 534 peaks (97.8%) were within ±1 bp from their parent allele peaks. Overall, the pull-up peaks toward adjacent shorter wavelength channels (e.g., from yellow to green) tended to be observed in the left side (shorter bp) of the corresponding parent allele peaks, and the opposite side tendency was observed for those pull-up peaks toward adjacent longer wavelength channels. These tendencies were also observed in the GlobalFiler data generated with the 3130xl and in the data obtained by injecting a J6 matrix standard with LIZ 500 or 600 v2 size standard into the 3500xL and 3130xl. Inspection of raw data revealed that the shift of pull-up peaks from their parent allele peaks was derived from sigmoid, pull-down, or slightly shifted pull-up shapes. Based on the obtained data, we propose a standard for assessment of questionable pull-up peaks.

Enhanced Static Noise Margin and Increased Stability SRAM Cell with Emerging Device Memristor at 45-nm Technology

Very Large Scale Integrated (VLSI) technology has conquered a momentous transformation and adaption. The glory of achieving these platforms goes to aspect ratio shrinking. Not only the dimensions are scaling down, but the revolution is forcing the designers to switch all circuits from one device level to another emerging devices. In this conflict, memristors are capable of making their roots stronger in VLSI domain as compared to other emerging devices. In this paper it is presented the research of static noise margin, highlighting the new fidelity issue i.e. the noise that has great impact on retention voltage of SRAM cell and this effect in memristive cell is less as compared to conventional 7T SRAM cell. Simulations and results have been performed and obtained from 7T SRAM and memristive 7T SRAM cell at 45 nm technology. In this paper, impact of the cell and pull-up ratio with their comparisons is also discussed.

Assessment of read and write stability for 6T SRAM cell based on charge plasma DLTFET

To overcome the process variations due to random dopant fluctuations (RDFs) and complex annealing techniques a charge plasma based doping less TFET (CP-DLTFET) device has been proposed for designing of 6T SRAM cell. The proposed device also benefited by subthreshold slope, low leakage current, and low power supply. In this paper, to avoid the dependency of stability parameters of SRAM cell to supply voltage (Vdd), here N-curve metrics has been analyzed to determine read and write stability. Because N-curve provides stability analysis in terms of voltage and current as well as it gives combine stability analysis with the facility of an inline tester. Further, analyzing the N-curve metrics for different Vdd, cell ratio, and pull-up ratio assist in designing the configuration of transistors for the better read and write stability. Power metrics of N-curve gives the knowledge about read and write stability instead of using four metrics (SINM, SVNM, WTV, and WTI) of N-curve. Finally, in the 6T CP-DLTFET SRAM cell, read and write stability is tested by the interface trap charges (ITCs). The performance parameter of the 6T CP-DLTFET SRAM cell provides considerable read and write stability with less fabrication complexity.

Low standby leakage 12T SRAM cell characterisation

ABSTRACTIn this work, a low power and variability-aware static random access memory (SRAM) architecture based on a twelve-transistor (12T) cell is proposed. This cell obtains low static power dissipation due to a parallel global latch (G-latch) and storage latch (S-latch), along with a global wordline (GWL), which offer a high cell ratio and pull-up ratio for reliable read and write operations and a low cell ratio and pull-up ratio during idle mode to reduce the standby power dissipation. In the idle state, only the S-latch stores bits, while the G-latch is isolated from the S-latch and the GWL is deactivated. The leakage power consumption of the proposed SRAM cell is thereby reduced by 38.7% compared to that of the conventional six-transistor (6T) SRAM cell. This paper evaluates the impact of the chip supply voltage and surrounding temperature variations on the standby leakage power and observes considerable improvement in the power dissipation. The read/write access delay, read static noise margin (SNM) and write SNM were evaluated, and the results were compared with those of the standard 6T SRAM cell. The proposed cell, when compared with the existing cell using the Monte Carlo method, shows an appreciable improvement in the standby power dissipation and layout area.

Design and analysis of noise margin, write ability and read stability of organic and hybrid 6-T SRAM cell

This paper analyzes SRAM cell designs based on organic and inorganic thin film transistors (TFTs). The performance in terms of static noise margin (SNM), read stability and write ability for all-p organic (Pentacene–Pentacene), organic complementary (Pentacene–C60) and hybrid complementary (Pentacene–ZnO) configurations of SRAM cell is evaluated using benchmarked industry standard Atlas 2-D numerical device simulator. Moreover, the cell behaviour is analyzed at different cell and pull-up ratios. The electrical characteristics and performance parameters of individual TFT used in SRAM cell is verified with reported experimental results. Furthermore, the analytical result for SNM of all-p organic SRAM cell is validated with respect to the simulated result. Besides this, the cell and pull-up ratios of the hybrid and organic SRAM cells are optimized for achieving best performance of read and write operations and thereafter, the results are verified analytically also. The SNM of hybrid cell is almost two times higher than the all-p SRAM, whereas this improvement is just 18% in comparison to the organic memory cell. On the other hand, the organic complementary SRAM cell shows an improvement of 26% and 22% for the read stability in comparison to the all-p organic and hybrid SRAM cells, respectively. Contrastingly, this organic cell demonstrates a reduction of 16% in the SNM and an increment of 76% in write access time in comparison to the hybrid cell. To achieve an overall improved performance, the organic complementary SRAM cell is designed such that the access transistors are pentacene based p-type instead of often used n-type transistor. Favorably, this organic SRAM design shows reasonably lower write access time in comparison to the cell with n-type access OTFTs. Moreover, this cell shows adequate SNM and read stability that too at substantially lower width of p-type access OTFTs.

Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively. Finally, the minimum operating voltages required for FD-SOI and bulk SRAM cells to meet the six-sigma yield requirement are compared.

Junctionless 6T SRAM cell

The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (IWR) of 33 µA along with a low leakage current (ILEAK) of 2 pA at a supply voltage (VDD) of 0.9 V for cell and pull-up ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.

Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron

This paper presents a performance comparison of a carbon nanotube-based field effect (CNFET)- and CMOS-based 6T SRAM cell at the 32nm technology node. HSPICE simulations, carried out using Berkeley predictive technology model (BPTM), show that for a cell ratio and pull-up ratio of 1, CNFET-based 6T SRAM cell provides an improvement of 21% in read static noise margin (SNM) at VDD=0.4V. The speed of CNFET cell is 1.84× that of CMOS cell. The standby leakage of CNFET cell is 84% less than CMOS cell. The process parameter variation results in 1.2% change in the read SNM of CNFET cell as compared with a wide variation of around 10.6% in CMOS cell.