Optimisation of SRAM cell in 7-nm node by response surface method

Abstract

ABSTRACT With CMOS process developing, the Static Random Access Memory (SRAM) suffers unavoidable degradation in terms of read and write stabilities. To optimise the memory with conventional 6-T cell in 7-nm process technology, Response Surface Method (RSM) is adopted to get the optimised relationship among the noise margin, the operating temperature, the supply voltage, the unit ratio, the pull-up ratio and the pre-charged voltage, et al. It shows that RSM approach is an effective statistical method for the optimisation of the SRAM cell, especially in the nano-scale scheme. In order to prove the superiority of the RSM approach, the noise margin variation is investigated from 90 nm to 7 nm technology nodes based on the general butterfly curves approach for the comparison. It shows that the stability of the SNM of the 6-T cell tends to be degraded with the continuous shrinkage of the process nodes. The RSM approach is demonstrated to be an effective way for the optimisation of the SRAM cell in single-digit nanometre node.