High Temperature Memory Design, Implementation, and Characterization in 1μm SiC CMOS Technology

Abstract

Abstract Electronic systems capable of withstanding high temperature environments are in high demand in various applications such as logging-while-drilling (LWD) systems and embedded electronics which are in the core of gas turbine engine controls. Designing memory that can process massive amounts of data in harsh environments while consuming low power opens doors for next generation, smart, high temperature electronic systems. In this work, a CMOS based six transistor (6T) static random-access memory (SRAM) cell is designed and implemented in a state-of-the-art SiC 1μm triple well CMOS process. The designed SiC SRAM cell performance has been characterized for different values of cell ratios (CR) [0.5, 0.6, 1, 1.5, 2, 2.5] and pull-up ratios (PR) [1, 2, 3, 4, 5, 6] to determine the cell size with optimal performance parameters. Static noise margin (SNM) values for the different combinations of CR and PR are calculated using the model developed by Seevinck, et. al. [13]. The highest SNM values observed at 25°C and 300°C are 4.71 V and 4.65 V, respectively. Read static noise margin (RSNM) values of 1.94 V and 1.90 V are achieved at 25°C and 300°C, respectively. Analysis of measured data shows that the optimum cell size is with a CR of 2.5 and a PR of 6. However, these results are significantly impacted by highly resistive ohmic contacts.