Pseudorandom Test Research Articles

An effective built-in self-test scheme for parallel multipliers

An effective built-in self-test (BIST) scheme for parallel multipliers (array and tree) is proposed. The new scheme combines the advantages of deterministic and pseudorandom testing and avoids their drawbacks. No modifications to the multiplier structure are required. A guaranteed very high fault coverage of a comprehensive cellular fault model is achieved. The results do not depend either on the gate-level implementation of the multiplier cells or the architecture of the multiplier (whether it is a carry-propagate or carry-save array multiplier or a tree multiplier) or on the multiplier size. A small deterministic test set of highly regular test vectors is used which exploits the inherent regularity of the multiplier architecture. The regularity of the test vectors allows for their on-chip generation with a very small hardware overhead, which is equivalent to the hardware overhead of pseudorandom testing.

GLFSR-a new test pattern generator for built-in-self-test

A new and effective pseudorandom test pattern generator, termed GLFSR, is introduced. These are linear feedback shift registers (LFSR's) over a Galois field GF(2/sup /spl delta//), (/spl delta/>1). Unlike conventional LFSR's, which are over GF(2), these generators are not equivalent to cellular arrays and are shown to achieve significantly higher fault coverage. Experimental results are presented in this paper depicting that the proposed GLFSR can attain fault coverage equivalent to the LPSR, but with significantly fewer patterns. Specifically, results obtained demonstrate that in combinational circuits, for both stuck-at as well as transition faults, the proposed GLFSR outperforms all conventional pattern generators. Moreover, these experimental results are validated by certain randomness tests which demonstrate that the patterns generated by GLFSR achieve a higher degree of randomless.

Theoretical properties of LFSRs for built-in self test

Linear Feedback Shift-Registers have been studied for a long time as interesting solutions for error detection and correction techniques in transmissions. In the test domain, and principally in Built-In Self Test applications, they are often used as generators of pseudo-random test sequences. Conversely, their potential to generate prescribed deterministic test sequences is dealt within more recent works, and nowadays, allows the investigation of efficient test with a pseudo-deterministic BIST technique. Pseudo-deterministic test sequences are composed of both deterministic and pseudo-random test patterns and offer high fault coverage with a tradeoff between test length and hardware cost. In this paper, synthesis techniques for LFSRs that embed such kind of sequences are described.

Optimization of bist resources during high-level synthesis

Lower bound estimations of functional resources at various stages of high-level synthesis have been developed to guide synthesis algorithms toward optimal solutions. In this paper we present lower bounds on the number of test resources (i.e., registers that generate pseudo-random test patterns and/or compress test responses) required to test a synthesized data path using built-in self-test (BIST). The bounds on different types of test resources are proved to be individually achievable and experiments show that in most cases the bounds can be achieved simultaneously and with minimum number of functional registers. Efficient ways of computing the lower bounds are developed. The estimations are performed on scheduled data flow graphs with a given module assignment and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of BIST resources to test itself.

Fault diagnosis of a logical circuit by use of a pseudorandom signal and a neural network

This paper describes a new method of pseudorandom testing of a digital circuit by use of a correlation method and a neural network. The authors have recently proposed a new method of fault diagnosis in a logical circuit by applying a pseudorandom M-sequence to the circuit under test, calculating the cross-correlation function between the input and the output, and comparing the cross-correlation functions with the references. This method, called the M-sequence correlation (MSEC) method, is further extended by using a neural network in order not only to detect the existence of faults, but also to find the place or location of the faults. The authors investigated the effects of using parts of the fault patterns to train the neural network to be able to detect faults. It is shown that more than 95% of faults can be detected even when only 60% of the possible training data are used.

Pseudorandom testing for mixed-signal circuits

In this paper, we propose a pseudorandom testing scheme for mixed-signal circuits. We first describe the pseudorandom testing technique for linear analog components and converters in mixed-signal circuits. With proper arithmetic operations on the responses to the random patterns, the impulse response of the device under test (DUT) can be constructed and used as the signature. By checking the constructed signatures against the derived tolerance ranges, we can infer the correctness of the DUT without explicitly measuring the original performance parameters. We also describe a technique of mapping the tolerance ranges in the performance space to its associated tolerance ranges in the signature space. The major advantages of our pseudorandom testing scheme are: (1) a universal input stimulus (white noise) is used and thus test generation can be avoided, (2) signatures for high quality testing can be easily constructed and thus testing cost can be minimized, and (3) the scheme can be used for Built-In Self-Test (BIST) implementation for DSP-based mixed-signal designs. We present simulation results to illustrate the effectiveness of the scheme.

Model-predictive control and real-time optimization of a cat cracker unit

A project for control and optimization of the Residual Catalytic Cracking Process at the Mongstad refinery is near completion. Four model-predictive control applications have been successfully implemented, using the IDCOM control software from Setpoint Inc. The most attractive feature of the controller is the well-defined control prioritizing hierarchy, and the linear impulse-response models have proved to give satisfactory performance on this process. Excitation and identification of the dynamic models proved to be a difficult task, and careful design and monitoring of the tests was mandatory in order to produce good results. Multi-variable Pseudo Random Binary Test Sequences were used for the excitation. Technical performance and operator acceptance of the new control functions have been good, but it is realized that a continuing effort is needed to fine-tune and maintain such functions. An on-line optimization function based on a static yield and quality model combined with an economic model is currently under work. An extensive program of planned experiments, with careful logging of measurements and laboratory results is now completed, and a hybrid model established by a combination of theoretical knowledge and regression techniques fits the process responses surprisingly well. The chosen model complexity seems to be very cost-effective for this purpose. The optimization is only local to the cracker plant. Prices for feeds and products have to be in accordance with the over-all refinery objectives to contribute to a global optimum. The new functions automate and integrate work and information transfer that were previously handled by procedures. This fact represents new demands for co-ordination and co-operation in the organization if the potentials of the new functions are to be fully exploited.

Oculomotor Pathology in Meniere's Disease

In this study data of voluntary eye movements 62 patients (mean age was 49.6 years) with Meniere's disease and 38 healthy control subjects were examined. Pseudo-random smooth pursuit (PRPEM) tests were conducted with frequency combination of 0.25 and 0.425 Hz. Saccades at constant targets and pseudo-randomly shifting targets were evaluated. In logistic regression analysis constant saccades correctly classified the cases in 57% as saccadic latency discriminating the groups best, latency being longer in Meniere group. In pseudo-random saccades, correct classification was achieved in 75.4% of all cases as latency discriminating the groups best, and latency was longer in Meniere group. In PRPEM, correct classification was achieved in 65.3% of all cases as gain by amplitude (GA), discriminating the groups best, and GA was smaller in Meniere group. Pseudo-random saccade test is a demanding task and that may explain why a peripheral vestibular lesion may interfere visual tracking and scanning performance. Latency is the most vulnerable of parameters to be lesioned. Results indicate that a peripheral vestibular lesion influences the control of voluntary eye movements and may explain the complaints of visual targeting on objects that patients with Meniere's disease have.

An Effective Multi-Chip BIST Scheme

This paper addresses the general problem of module level test of assembled Multi-Chip Modules (MCMs) and specifically the performance test of such modules. It presents a novel solution based-on built-in self-test (BIST). This solution augments the conventional single-chip BIST approach, which is used to produce individual good dies, to an effective multi-chip BIST solution. The multi-chip BIST puts the entire module in a self-test mode. The self-test mode not only provides effective detection of static and dynamic faults, but also identifies the failed elements, i.e., bad dies or substrate. The multi-chip self-test scheme is based on pseudo-random test generation and uses multi-signature evaluation. The hardware design of multi-chip and single-chip self-test blocks is combined under one common architecture called the Dual BIST Architecture. The paper introduces the Dual BIST Architecture and demonstrates a set of design configurations to implement it. The presented BIST solution provides a reliable static and dynamic test at the module as well as the bare die levels.

Arithmetic built-in self-test for DSP cores

A new built-in self-test (BIST) methodology is presented in which all generation and compaction functions are executed by basic building blocks such as adders, ALU's, and multipliers, performing regular arithmetic functions in digital signal processing (DSP) cores. It is demonstrated how these components are themselves tested, and subsequently used to perform more complex testing functions. The need for extra hardware is either entirely eliminated or drastically reduced, test vectors can be easily distributed to different modules of the system, test responses can be collected in parallel, and there is virtually no performance degradation. As an integral part of the proposed BIST environment, arithmetic two-dimensional (2-D) generators of pseudorandom test vectors are also introduced to further integrate the scheme with parallel scan and boundary scan designs used to test peripheral devices of the core.

Accurate system identification using inputs with imperfect autocorrelation properties

The application of periodic pseudorandom sequences to system identification via input-output crosscorrelation is well established. Accurate estimates of system impulse response can be obtained if the pseudorandom test signal has a perfect (impulsive) periodic autocorrelation function. The authors present theoretical results which show that it is also possible to use sequences with imperfect autocorrelation functions as test inputs while maintaining identification accuracy. Simulation results are provided which verify the theoretical basis of this method.

Statistical analysis of multiple intermittent faults in combinational circuits

Statistical analysis of multiple intermittent faults (SAMIFs) is proposed as a method for estimating the detection probabilities and fault coverage of multiple intermittent faults in combinational circuits. SAMIFs involves the concurrent simulation of multiple intermittent faults and an estimation of the controllability and observability values for each node of the faulty circuit for a given set of input vectors. The controllabilities and observabilities are then used to derive estimates of the fault-detection probabilities and the overall fault coverage. An algorithm for estimating the fault coverage of a pseudo-random test vector set over a set of multiple intermittent faults in a combinational circuit is also proposed. Experimental results obtained from applying the algorithm to a number of benchmark circuits are also presented.

Test response compaction using multiplexed parity trees

Built-in self-testing requires test response streams from many observation points to be merged (space compaction) and compressed (time compaction) into a short signature. The compaction circuits should be transparent to error propagation in order to minimize aliasing, which occurs when a faulty response maps to the fault-free signature. We investigate the use of multiplexed parity trees (MPTs) for zero-aliasing space compaction. MPTs combine the error propagation properties of multiplexers and parity trees, and ensure zero aliasing via multistep compaction. We present two design techniques based on MPTs-output selection and fanout insertion-that eliminate aliasing for both deterministic and pseudorandom test sets. Our experiments with the ISCAS benchmark circuits show that zero aliasing can be achieved with small test sets and moderate hardware overhead. We also demonstrate that a very high percentage of single stuck-line faults in the compaction circuit are detected by the test patterns applied to the circuit under test.

Realizing a high measure of confidence for defect level analysis of random testing [VLSI

The defect level in circuit testing is the percentage of circuits, such as chips, which are defective and shipped for use after testing. In this work, it is demonstrated that the defect level of testing a circuit using random patterns should have a probability distribution rather than just a single value. Based on this concept, the confidence degree of a specified defect level for random testing can be derived, and the quality of circuit random testing is thus guaranteed. Results obtained based on random testing can be extended to other test methods, e.g., deterministic testing, pseudo-random testing, or functional testing. Experiments using computer simulation have been conducted for this work, and the results are very encouraging.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Test embedding with discrete logarithms

When using Built-In Self Test (BIST) for testing VLSI circuits, a major concern is the generation of proper test patterns that detect the faults of interest. Usually a linear feedback shift register (LFSR) is used to generate test patterns. We first analyze the probability that an arbitrary pseudo-random test sequence of short length detects all faults. The term short is relative to the probability of detecting the fault having the fewest test patterns. We then show how to guide the search for an initial state (seed) for a LFSR with a given primitive feedback polynomial so that all the faults of interest are detected by a minimum length test sequence. Our algorithm is based on finding the location of test patterns in the sequence generated by this LPSR. This is accomplished using, the theory of discrete logarithms. We then select the shortest subsequence that includes test patterns for all the faults of interest, hence resulting in 100% fault coverage. >

Avoiding linear dependencies in LFSR test pattern generators

Linear Feedback Shift Registers (LFSRs) constitute a very efficient mechanism for generating pseudoexhaustive or pseudo-random test sets for the built-in self-testing of digital circuits. However, a well-known problem with the use of LFSRs is the occurrence of linear dependencies in the generated patterns. In this paper, we show for the first time that the amount of linear dependencies can be controlled by selecting appropriate characteristic polynomials and reordering the LFSR cells. We identify two classes of such polynomials which, by appropriate LFSR cell ordering, guarantee that a large ratio of linear dependencies cannot occur. Experimental results show significant enhancements on the fault coverage for pseudo-random testing and support the theoretical relation between minimization of linear dependencies and effective fault coverage.

On shortening test sequence length for signature analyzer

Based on the built-in self-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register. The test length for the worst faults can be obtained by analyzing compressed signature. Finally, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.

Pseudo random smooth pursuit test in patients with acoustic neuroma.

We examined the pseudo random smooth pursuit test in patients with cerebellopontine angle (CPA) tumors. Four different frequency combinations of sinusoids 0.15-0.35 Hz, 0.25-0.425 Hz, 0.3-0.7 Hz and 0.45-0.7 Hz were tested. Gain was calculated by comparing the smooth pursuit amplitude with stimulus after the supporting saccades had been removed. Phase was calculated by comparing maximum excursion of the eyes and stimulus. Gain was in the patients lower than in the controls in different frequency combinations, and the difference was statistically significant/highly significant in different frequency combinations. In the phase shift the differences were highly significant in the two higher frequency combinations and significant in the second frequency combination (0.25-0.425 Hz), while in the first frequency combination (0.15-0.35 Hz) the difference was not significant. The gain method was a somewhat better analyzing method than the phase shift method.

A practical nonlinear model for magnetic recording channels

In this paper, a practical nonlinear model for high density magnetic recording channels is proposed. Unlike previous Volterra series methods, this model can be constructed based on simple measurements of the isolated transition response and dibit responses. The experimental results show that the proposed nonlinear model accurately predicts the channel output over the entire length of the 1023-bit maximum length pseudo-random binary testing sequence. >

3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits

A method for weighted pseudorandom test generation based on a deterministic test set is described. The main advantages of the method described over existing methods are: (1) only three easily generated weights (0, 0.5 and 1) are used, (2) a minimum number of shift register cells is used, thus leading to minimal hardware for built-in-test applications, and (3) the weights are selected to allow the same coverage of target faults attained by the deterministic test set to be attained by weighted random patterns. The weights are computed by walking through the range of test generation approaches from pure random at one extreme to deterministic at the other extreme, dynamically selecting the weight assignments to correspond to the remaining faults at every stage. Hardware suitable for the generation of random patterns under the proposed method is described. The method is suitable for both combinational and sequential circuits. Experimental results are provided for ISCAS-85 and MCNC benchmark circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>