An effective built-in self-test scheme for parallel multipliers

Abstract

An effective built-in self-test (BIST) scheme for parallel multipliers (array and tree) is proposed. The new scheme combines the advantages of deterministic and pseudorandom testing and avoids their drawbacks. No modifications to the multiplier structure are required. A guaranteed very high fault coverage of a comprehensive cellular fault model is achieved. The results do not depend either on the gate-level implementation of the multiplier cells or the architecture of the multiplier (whether it is a carry-propagate or carry-save array multiplier or a tree multiplier) or on the multiplier size. A small deterministic test set of highly regular test vectors is used which exploits the inherent regularity of the multiplier architecture. The regularity of the test vectors allows for their on-chip generation with a very small hardware overhead, which is equivalent to the hardware overhead of pseudorandom testing.