An Effective Multi-Chip BIST Scheme

Abstract

This paper addresses the general problem of module level test of assembled Multi-Chip Modules (MCMs) and specifically the performance test of such modules. It presents a novel solution based-on built-in self-test (BIST). This solution augments the conventional single-chip BIST approach, which is used to produce individual good dies, to an effective multi-chip BIST solution. The multi-chip BIST puts the entire module in a self-test mode. The self-test mode not only provides effective detection of static and dynamic faults, but also identifies the failed elements, i.e., bad dies or substrate. The multi-chip self-test scheme is based on pseudo-random test generation and uses multi-signature evaluation. The hardware design of multi-chip and single-chip self-test blocks is combined under one common architecture called the Dual BIST Architecture. The paper introduces the Dual BIST Architecture and demonstrates a set of design configurations to implement it. The presented BIST solution provides a reliable static and dynamic test at the module as well as the bare die levels.