Pseudo-random Pattern Generator Research Articles

A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress

Burn-In test equipment usually owns extensive memory capabilities to store pre-computed patterns to be applied to the circuit inputs as well as ad-hoc circuitries to drive and read the DUT pins during the BI phase. The solution proposed in this paper dramatically reduces the memory size requirement and just demands a generic microcontroller unit (MCU) equipped with a couple of embedded processors, some standard common peripheral units, and a few KB memories. Moreover, the proposed Burn-In tester could be integrated into a System Level Test equipment which is typically based on MCUs to communicate functionally with the DUT. This paper provides full details about the architecture of such a low-cost innovative tester, which can supply the DUT with unlimited pseudo-random patterns created autonomously by the MCU firmware from any selected seed. The tester prototype developed to collect experimental results includes a low-cost System-on-Chip based on a multi-core MCU and a set of peripheral cores, encompassing timers and Direct Memory Access modules. The tester prototype is used to stress an automotive chip accounting for about 20 million gates, 700 thousand scan flip-flops, and several scan modes. The combination of pseudo-random pattern generation with the ability to control different scan and Design for Testability (DfT) modes, including LBIST, permits to reach a higher coverage of stress metrics than by the application of a limited set of pre-computed ATPG patterns. The toggle coverage level reached is up to 95.89%. The application speed achieved by the tester with non-optimized connections is up to about 10MHz.

Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment Testing.

To improve the test accuracy and fault coverage of high-speed railway-related equipment boards, a time-varying pseudorandom disturbance algorithm based on the automatic test pattern generation technology in chip testing is proposed. The algorithm combines the pseudorandom pattern generation algorithm with the deterministic pattern generation D algorithm. The existing pseudorandom number generation method usually requires random seeds to generate a series of pseudorandom numbers. In this algorithm, the system timer is used as the random seed to design a pseudorandom pattern generation method of time-varying seed to improve the randomness of pseudorandom pattern generation. In addition, in combination with the D algorithm, this work proposes a new switching logic between two algorithms by counting invalid pattern proportions. When the algorithm is applied to track a circuit netlist, the fault coverage can reach near 100%. However, the large-scale circuit fault coverage cannot easily reach 100%. The test results for the standard circuits of different sizes show that at the same time, compared with the independent pattern generation methods, the proposed algorithm can improve fault coverage by more than 50% and 30% and significantly improve the pattern generation efficiency. Therefore, it can be used perfectly in the subsequent construction of high-speed railway equipment test platforms.

A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT-LFSR-TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.

Design of a 1.9 GHz low-power LFSR Circuit using the Reed-Solomon Algorithm for Pseudo-Random Test Pattern Generation

A linear feedback shift register (LFSR) has been frequently used in the Built-in Self-Test (BIST) designs for the pseudo-random test pattern generation. The higher volume of the test patterns and the lower test power consumption are the key features in the large complex designs. The motivation of this study is to generate efficient pseudo-random test patterns by the proposed LFSR and to be applied in the BIST designs. For the BIST designs, the proposed LFSR satisfied with the main strategies such as re-seeding and lesser test power consumption. However, the reseeding approach was utilized by the maximum-length pseudo-random test patterns. The objective of this paper is to propose a new LFSR circuit based on the proposed Reed-Solomon (RS) algorithm. The RS algorithm is created by considering the factors of the maximum length test patterns with a minimum distance over the time t. Also, it has been achieved an effective generation of test patterns over a stage of complexity order O (m log2 m), where m denotes the total number of message bits. We analysed our RS LFSR mathematically using the feedback polynomial function to decrease the area overhead occupied in the designs. The simulation works of the proposed RS LFSR bit-wise stages are simulated using the TSMC 130 nm on the Mentor Graphics IC design platform. Experimental results showed that the proposed LFSR achieved the effective pseudo-random test patterns with a lower test power consumption of 25.13 µW and 49.9 µs. In addition, proposed LFSR along with existing authors’ LFSR are applied in the BIST design to examine their power consumption. Ultimately, overall simulations operated with the highest operating frequency environment as 1.9 GHz.

Implementation and Utilization of LBIST for 16 bit ALU

This paper refers to implementation of Low Power Built-In-Self-Test (LBIST) and its utilization for testing of 16 bit ALU core. Low Power Test Pattern (LP) Generator is programmable and able to produce pseudorandom test patterns. The programmability feature brings in selectiveness in toggling levels of test patterns. This helps to increase the error coverage gradient. This low power pattern generator consists of a pseudo random pattern generator (PSPR) which can be a linear feedback shift register or ring generator. The test pattern generator allows the production of binary sequences by devices with that selected toggling rate is defined as ‘Preselected toggling’ (PRESTO) activity. In this methodology, controls for operation of generator are selected automatically. Selection of all the controls is made simple and accurate for the tuning. Using this method fault coverage of test pattern generator can be improved as well as pattern count ratio gets improved. The proposed low power test compression method helps to get predictable test patterns. Here preselected toggling based logic BIST is used to get flexible and accurate test patterns hence high quality testing is achieved here with integration of PRESTO and LBIST method.

Design of Low Transition Pseudo-Random Pattern Generator for BIST Applications

Built in self testing (BIST) is most attractive technique to test different kind of circuits. In BIST, test patterns are generated by different techniques of test pattern generation and applied to the circuit under test (CUT). In pseudorandom BIST architecture, test patterns are generated by Linear Feedback Shift Register (LFSR). Due to high Switching in pattern generation by conventional LFSR, power dissipation is high in conventional LFSR. Power is an important constraint in VLSI (Very Large Scale Integration) testing. This paper presents a modification in LFSR to generate pattern for BIST applications with reduced power requirement. This new technique represent low transition pattern pseudorandom generator (LT-PRG) for Test-perClock and Test-per-Scan BIST applications. The LT-PRPG is designed with the use of a LFSR and a 2x1 multiplexer. Experimental results show that the implementation of BitSwapping LFSR can reduce the internal transition activity probability which directly affect the dissipation of power in CUT without affecting the fault coverage.

FPGA Implementation of an LFSR based Pseudorandom Pattern Generator for MEMS Testing

strides in programmable logic density, speed and hardware description language (HDL) have empowered the engineer with the ability to implement high-performance digital functionality within field programmable gate array (FPGA). Linear feedback shift resister (LFSR) has become one of the central elements used in testing and self testing of contemporary complex electronic systems like processors, controllers and integrated circuits (ICs). This paper presents the FPGA implementation of an LFSR based pseudorandom pattern generator. This LFSR has the characteristics of high speed, low power consumption and it is especially suited in processing environment where uniform distribution random numbers are required. A typical application of the pattern generator considered in this work is the testing of micro- electro-mechanical-system (MEMS), where low power consumption is required. Very high speed integrated circuit HDL (VHDL) was used to implement the LFSR on FPGA. A testbench in VHDL was used to verify the correctness of the design. The compiled VHDL code was been synthesized into gate level. Area and timing optimization were done to achieve a very low gate count of 436 and increase the design speed to 178MHz Mentor Graphics and Xilinx ISE 6, electronic design automation (EDA) tool suite and DIGILENT D2SB PROTO BOARD were used for the overall FPGA implementation process.

Optimising pseudo‐random built‐in self‐testing of fully synchronous as well as multisynchronous networks‐on‐chip

Most built-in self-test architectures use pseudo-random test pattern generators. However, whenever this technique has been applied to on-chip interconnection networks, overly large testing latencies have been reported. On the other hand, alternative approaches either suffer from large area penalties (like scan-based testing or the use of deterministic test patterns) or poor fault coverage in the control path (functional testing). Moreover, the recent proliferation of clock domains on a chip makes testing overly challenging. This manuscript presents the optimisation of a built-in self-testing framework based on pseudo-random test patterns to the microarchitecture of network-on-chip switches. As a result, fault coverage and testing latency approach those achievable with deterministic test patterns while materialising relevant area savings and enhanced flexibility. Finally, the authors implement the extension of the proposed testing methodology to multisynchronous systems, thus making it compliant with the relaxation of synchronisation assumptions in nanoscale designs.

Cost Optimized Design Technique for Pseudo-Random Numbers in Cellular Automata

In this research work, we have put an emphasis on the cost effective design approach for high quality pseudo-random numbers using one dimensional Cellular Automata (CA) over Maximum LengthCA. This work focuses on different complexities e.g ., space complexity, time complexity, design complexity and searching complexity for the generation of pseudo -random numbers in CA. The optimization procedure for these associated complexities is commonly referred as the cost effective generation approach for pseudorandom numbers. The mathematical approach for proposed methodology over the existing maximum length CA emphasizes on better flexibility to fault coverage. The randomness quality of the generated patterns for the proposed methodology has been ve rified using Diehard Tests which reflects that the randomness quality achieved for proposed methodology is equal to the quality of randomness of the patterns generated by the maximum length cellular automata. The cost effectiveness results a cheap hardware implementation for the concerned pseudo-random pattern generator. Short version of this paper has been published in [1].

Peak- and Average-Power Reduction in Check-Based BIST by using Bit-Swapping LFSR and Check-Chain Ordering

In this paper the proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 × 1 multiplexer. When used to generate test patterns for check-based built-in self-tests, it reduces the number of transitions that occur at the check-chain input during check shift operation by 50% when compared to those patterns produced by standard LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications. The BS-LFSR is combined with a check chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (check and capture) in the test cycle or while checking out a response to a sign pattern analyzer. These techniques have a substantial effect on average- and peak-power reductions with negligible effect on fault coverage or test application time. Experimental results bench mark circuits show up to 65% and 55% reductions in average and peak power, respectively. Keywords: Built-in self-test (BIST), linear feedback shift register (LFSR), low-power test, pseudorandom pattern generator, scan-chain ordering,

An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation

This paper presents a novel seed-based test pattern generator (SB-TPG). The core of SB-TPG is a seed sequence generator. A coverage-driven seed generation algorithm has been proposed to generate the optimized seeds. The test sequence generated by SB-TPG is a single input change (SIC) sequence that can significantly reduce test power for test-per-clock built-in self-test (BIST). Further, seed-masking technique has been put forward to filter those power-consuming seeds, thus reducing test power for test-per-scan BIST. Experimental results show that SB-TPG can achieve high fault coverage with short test length, low power and small hardware overhead.

대형 건축물과 주거 친화형 저 풍속 연곡형 적층 풍력발전 시스템에 관한 연구

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.

A scan disabling-based BAST scheme for test cost reduction

This paper proposes a scan disabling-based BIST-aided scan test (BAST) scheme. In this scheme, a pseudo-random pattern generator(PRPG) generates test vector for each slice in multiple scan chains. Using scan disabling technique, the generated test vector is shifted into the scan chains until it is compatible with its corresponding slice for a deterministic test set with don't care bits. An automatic test equipment (ATE) only needs to store the control signals instead of test data. The proposed scheme that is based on the standard scan and uses any test set with don't care bits is widely applicable and easy to deploy. Its hardware overhead that is a PRPG, phase shifter, MISR and scan disable signal is very low. Theoretical analysis and experimental results show the proposed scheme can achieve higher compression gain compared with previous low cost scheme when care bits are few.

페이지 쉬프터 기반의 의사 난수 패턴 생성기

패턴생성기로 LFSR(linear feedback shift register)은 기계 자체에 고유의 선형의존성이 있어 패턴을 생성함에 있어 비트의 위치를 이동시켜 수열을 생성하기 때문에 생성되는 패턴들의 상관관계가 높고 따라서 오류 검출률이 낮아지게 된다. 이런 문제점을 해소하기 위하여 scan chain 사이에 XOR 게이트의 조합으로 구성된 페이지 쉬프터를 장착하여 출력 테스트 패턴의 난수성을 높임으로써 LFSR 고유의 선형의존성을 줄이고 오류 검출률을 높이는 연구가 활발히 진행되어 왔다. 본 논문에서는 PRPG(pseudo random pattern generator)로서 특성 다항식을 원시다항식으로 갖는 LFSR을 사용하여 어떤 임의의 두 채널에서 출력되는 이진 수열의 선형 의존성을 줄이기 위한 방법으로 적절한 탭 수를 유지하며 최소의 위상이동차를 보장하는 페이지 쉬프터를 갖는 LFSR 기반의 PRPG를 구성하는 방법을 제안한다. 제안된 알고리즘에 따라 페이지 쉬프터를 구성하면 기존의 방법보다 페이지 쉬프터를 훨씬 빨리 구성 할 수 있는 장점이 있다. Since an LFSR(linear feedback shift register) as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG(pseudo random pattern generator).

A Scalable Test Structure for Multicore Chip

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper reports an efficient synthesis scheme for pseudorandom pattern generators (PRPGs) of arbitrary length. The <formula formulatype="inline"> <tex Notation="TeX">$n$</tex></formula>-bit PRPG, synthesized in linear time <formula formulatype="inline"><tex Notation="TeX">$(O(n))$</tex></formula>, generates quality pseudorandom patterns leading to a highly efficient test logic for the very-large-scale integration (VLSI) circuit. The cascadable structure of proposed <formula formulatype="inline"><tex Notation="TeX">$n$</tex></formula>-cell PRPG is utilized to construct the <formula formulatype="inline"><tex Notation="TeX">$(n+1)$</tex> </formula>-cell PRPG, in two time steps, without sacrificing the pseudorandomness quality. This eases the design of on-chip test pattern generators for the system-on-a-chip implementing multiple cores. It avoids the requirement of disparate test hardware for different cores and thereby ensures drastic reduction in the cost of test logic. The effective characterization of nonlinear cellular automata (CA) provides the foundation of such a design. Extensive experimentation confirms the better efficiency of the proposed test structure compared to that of the conventional designs, developed around maximal length CA/linear feedback shift register of <formula formulatype="inline"><tex Notation="TeX">$O(n^{3})$</tex> </formula> complexity. </para>

Non-linear test pattern generators for built-in self-test

Various linear finite state machines have been widely used as pseudo-random test pattern generators for the built-in self-test of integrated circuits. These generators are inexpensive to use as they have the advantage of low hardware overhead. However, the Geffe generator, a classic type of non-linear finite state machine, has not been frequently studied or used in similar applications. It is known that a Geffe generator, when used as a pattern generator for digital system testing gives improved fault detection. Unfortunately, the area overhead involved is sufficiently high, thus, such a generator becomes impractical for built-in self-test. To solve such problems, we introduce two possible new designs of the Geffe generator. These new designs are based on the generator's original architecture, so they preserve the non-linear structure. Our optimal goal is to achieve a very sharp reduction of the area overhead, and maintain a satisfactory fault detection capability. These two new designs are exercised in the fault simulations of benchmark sequential circuits. The experimental results demonstrate both of our designs can lead to fault coverage, which significantly exceeds the fault coverage of linear machines, and is comparable to the original Geffe generator.

A fast seed selection technique for cost effective hybrid pattern generation

In this paper, a fast seed selection implementation procedure for LFSR based pseudorandom pattern generation in hybrid technique is described. This selection technique reduced the pseudo-random patterns to detect most of the easy-to-detect faults. The stored patterns are then used to detect remaining hard-to-detect faults. Fast cost calculation methodology is used to determine the optimum ratio of pseudo-random and stored patterns in the hybrid technique. This process is able to execute fast 100% fault detection with minimum test time for both VLSI chip and system- on-chip (SoC) testing. The fault simulation results using pseudo-random patterns with the fast seed selection technique showed significant number of test patterns reduction (>50%) compared to reseeding technique. The stored patterns also detected the rest of the hard-to-detect faults with reduced number of patterns (<100). Fault simulation experiments both on pseudo-random and stored patterns in the hybrid technique also showed on the average better results than previous works (pseudo-random >40% and deterministic >20%).

Maximum sequence test pattern generators with irreducible characteristic polynomials

Abstract Mechanisms that can generate maximum-length sequences (M-sequences) are of particular interest in pseudoexhaustive or pseudorandom built-in Test Pattern Generation (TPG). The characteristic polynomial of these mechanisms is restricted to be chosen among primitive polynomials only, since the latter require only one initialization state (seed). Recently, it was shown that any non-primitive irreducible polynomial can be used as characteristic polynomial to generate an M-sequence in the minimum number of cycles and with hardware overhead bounded by a low constant irrespectively of the number of seeds. In this paper, we describe and analyze the hardware overhead of two alternative schemes for the same purpose. These schemes offer even lower hardware overhead than the original one for a large majority of non-primitive irreducible polynomials of each degree. We also catalog each non-primitive irreducible polynomial of degree 12–22 according to the least costly of these schemes that can be used with it to generate an M-sequence.

Phase Shifter Merging

Phase shifters are used in conjunction with Linear Feedback Shift Registers and Cellular Automata in order to impose sufficient channel separations on the bit sequences produced by their successive cells. The aim is to reduce structural correlations and/or linear dependencies that are problematic for pseudorandom and pseudoexhaustive built-in test pattern generation (TPG). In this paper we present a synthesis approach that merges the logic of the original TPG mechanism with that of the required phase shifter network and yields a new compact structure that can offer lower area overhead and improved frequency of operation than the existing approach.

Optimized reseeding by seed ordering and encoding

Mixed-mode logic built-in self-test (BIST) applies both pseudorandom test patterns and deterministic test patterns [from an automatic test pattern generation (ATPG) tool] to the combinational portion of the circuit under test. Each scan-test cycle consists of: 1) shifting a test pattern into the scan chains; 2) capturing the response to that pattern; and 3) shifting the captured response out of the scan chains. The shifting of the test pattern out of the scan chains is overlapped with shifting in the next test pattern. The pattern shifted into the scan chains comes from the output of the pseudorandom pattern generator (PRPG); this pattern is determined by the initial state or seed of the PRPG (the contents of the PRPG at the beginning of the shifting operation). In a pseudorandom cycle, the initial state is the final state (last PRPG contents) from the previous cycle. The initial state of a deterministic cycle is shifted into the PRPG either from an a tester or from an on-chip BIST controller. This paper describes techniques to minimize the number of deterministic seeds that must be used: the number of seeds determines the required storage either on the ATE or the chip being tested. These techniques interleave pseudorandom and deterministic cycles rather than first applying all of the pseudorandom cycles and then the deterministic cycles. The decision of when to change from a pseudorandom cycle to a deterministic cycle is made by comparing the final state of the pseudorandom cycle with previously generated ATPG patterns or by carrying out fault simulation on the final state. Which deterministic pattern is chosen for the deterministic cycle critically influences the remainder of the test. A methodology for doing this is described. In addition to interleaving test cycles, it is possible to use partial cycles in which the PRPG operates for a few clocks without loading the scan chains. This allows a new seed to be present without loading the seed from the ATE or controller. As might be suspected, this reduces the number of stored seeds at the penalty of more complexity in the control sequence. These techniques were simulated and compared with conventional reseeding for some ISCAS'89 benchmarks. Improvements varied between 25% and 85% in the required seed storage.