Abstract
Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT-LFSR-TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.
Highlights
Digital cores that are currently incorporated into advanced and up-to-date Systems on Chip (SoC) usually include Logic Built-In Self-Test (Logic BIST, LBIST) modules
Other parameters that are essential for any test pattern generator include the maximum operational frequency and the cost of hardware implementation, expressed, for instance, as the area of silicon surface occupied by the Test Pattern Generator (TPG) or as the number of equivalent two-input NAND gates
Variations of parameters for the VHDL model make it possible to set up both the register length and the number of configurable D/T flip-flops included in the register, while the MODE signal shown in Figure 13a is dedicated to controlling the operation mode for the entire DT-Linear Feedback Shift Register (LFSR) register module
Summary
Digital cores that are currently incorporated into advanced and up-to-date Systems on Chip (SoC) usually include Logic Built-In Self-Test (Logic BIST, LBIST) modules. A very popular LBIST architecture operated in the test-per-scan mode is STUMPS (Self-Test Using MISR/Parallel Shift register sequence generator) [1,2] The structural diagram of a typical LBIST module with the STUMPS architecture as depicted in Figure 1 includes some key components, such as a generator of pseudo-random tests, or a Pseudo-Random Pattern Generator (PRPG) and a Multi-Input Signature Register (MISR). Responses to test vectors gathered from outputs of a CUT are loaded in the parallel mode into scan paths, and scan paths are switched to the serial mode and information from all scan paths is supplied to inputs of the MISR module where information is subject to compaction (lossy compression).
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
