Peak- and Average-Power Reduction in Check-Based BIST by using Bit-Swapping LFSR and Check-Chain Ordering

Abstract

In this paper the proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 × 1 multiplexer. When used to generate test patterns for check-based built-in self-tests, it reduces the number of transitions that occur at the check-chain input during check shift operation by 50% when compared to those patterns produced by standard LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications. The BS-LFSR is combined with a check chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (check and capture) in the test cycle or while checking out a response to a sign pattern analyzer. These techniques have a substantial effect on average- and peak-power reductions with negligible effect on fault coverage or test application time. Experimental results bench mark circuits show up to 65% and 55% reductions in average and peak power, respectively. Keywords: Built-in self-test (BIST), linear feedback shift register (LFSR), low-power test, pseudorandom pattern generator, scan-chain ordering,