A Scalable Test Structure for Multicore Chip

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper reports an efficient synthesis scheme for pseudorandom pattern generators (PRPGs) of arbitrary length. The <formula formulatype="inline"> <tex Notation="TeX">$n$</tex></formula>-bit PRPG, synthesized in linear time <formula formulatype="inline"><tex Notation="TeX">$(O(n))$</tex></formula>, generates quality pseudorandom patterns leading to a highly efficient test logic for the very-large-scale integration (VLSI) circuit. The cascadable structure of proposed <formula formulatype="inline"><tex Notation="TeX">$n$</tex></formula>-cell PRPG is utilized to construct the <formula formulatype="inline"><tex Notation="TeX">$(n+1)$</tex> </formula>-cell PRPG, in two time steps, without sacrificing the pseudorandomness quality. This eases the design of on-chip test pattern generators for the system-on-a-chip implementing multiple cores. It avoids the requirement of disparate test hardware for different cores and thereby ensures drastic reduction in the cost of test logic. The effective characterization of nonlinear cellular automata (CA) provides the foundation of such a design. Extensive experimentation confirms the better efficiency of the proposed test structure compared to that of the conventional designs, developed around maximal length CA/linear feedback shift register of <formula formulatype="inline"><tex Notation="TeX">$O(n^{3})$</tex> </formula> complexity. </para>