Design of an on-chip test pattern generator without prohibited pattern set (PPS)

Abstract

This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The on-chip TPG is so designed that it generates test patterns while avoiding generation of a given Prohibited Pattern Set (PPS). The design ensures the desired pseudo-random quality of the test patterns generated. The experimental results confirm the high quality of randomness while ensuring fault coverage close to the figures achieved with a typical Pseudo Random Pattern Generator (PRPG) designed around maximal length LFSR/CA. Compared to the conventional PRPG, our method incurs no additional cost.