A fast seed selection technique for cost effective hybrid pattern generation

Abstract

In this paper, a fast seed selection implementation procedure for LFSR based pseudorandom pattern generation in hybrid technique is described. This selection technique reduced the pseudo-random patterns to detect most of the easy-to-detect faults. The stored patterns are then used to detect remaining hard-to-detect faults. Fast cost calculation methodology is used to determine the optimum ratio of pseudo-random and stored patterns in the hybrid technique. This process is able to execute fast 100% fault detection with minimum test time for both VLSI chip and system- on-chip (SoC) testing. The fault simulation results using pseudo-random patterns with the fast seed selection technique showed significant number of test patterns reduction (>50%) compared to reseeding technique. The stored patterns also detected the rest of the hard-to-detect faults with reduced number of patterns (<100). Fault simulation experiments both on pseudo-random and stored patterns in the hybrid technique also showed on the average better results than previous works (pseudo-random >40% and deterministic >20%).