Ps Rms Research Articles

Design and characterization of the FAST chip: a front-end for 4D tracking systems based on Ultra-Fast Silicon Detectors aiming at 30 ps time resolution

Detectors able to measure the time of flight with very high accuracy (∼10 ps RMS) are becoming fundamental in the design of new High Energy Physics experiments, where accurate time measurements will be used to mitigate pileup effects. The development of such detectors has spurred intense R&D in both silicon sensors and the associated readout electronics, aiming at obtaining silicon-based detectors with a time resolution in the few tens-of-picosecond range. This work presents FAST, a family of three different 20 channel amplifier-comparator chips, tailored to the readout of Ultra Fast Silicon Detectors. These ASICs have been designed optimizing the sensor-readout interplay with the aim of reaching the smallest possible jitter term. The three chips of the FAST family differ in the architecture of the front-end while sharing the channel back-end, consisting of a leading-edge discriminator and a LVDS driver. The goal of these front-ends is to achieve a time resolution of about 30 ps RMS while coupled to a sensor with a few pico-Farad capacitance, keeping the power budget of the single channel below 1.3 mW. This paper reports the description of the FAST design architecture and summarizes the results on the initial characterization of one chip of the FAST family, in a stand-alone test structure and when coupled to a UFSD.

Feasibility Study of Upgrades to the PLS-II Storage Ring

The PLS-II is a third-generation light source; it has been operating since 2011. It has a double-bend structure with non-zero dispersion along the straight section. Here, we assess three proposed upgrades to the PLS-II. First, we evaluate use of a canted insertion device beamline to increase the number of beamlines. Second, we evaluate the consequences of upgrading the bending magnet to a superbend magnet; the change doubles the strength of the bending field and increases the critical energy from 8.7 keV to 17 keV. Finally, a short-bunch mode for time-resolved experiments is studied; the goal is to achieve a bunch length of 5 ps rms by using a low-alpha mode and increasing the RF gap voltage.

A high speed BiCMOS comparator ASIC with voltage adjustable hysteresis

A design of high-speed comparator ASIC, fabricated in 0.35μm SiGe BiCMOS process is presented. This ASIC is designed as a part of the front-end readout electronics development for Resistive Plate Chamber detector of Iron Calorimeter experiment of India based Neutrino Observatory. The ASIC comprises eight channels of high-speed voltage comparator with LVDS driver. A novel technique is used to implement a small voltage adjustable hysteresis in the comparator without additional power, area and circuit complexity. This ASIC multiplexes input analog signals through an on-chip high-speed 50 Ω cable driver. The analog multiplexer supports daisy and non-daisy modes for access of input signals. The ASIC has power consumption of ∼ 13 mW/channel. The comparator LVDS output rise time is ∼ 900 ps. The measured timing precision of the ASIC is ∼ 40 ps RMS.

Setup and Characteristics of a Timing Reference Signal with sub-ps Accuracy for AWAKE

We describe a method to overcome the triggering jitter of a streak camera to obtain less noisy images of a self-modulated proton bunch over long time scales (~ 400 ps to ns) with the time resolution (~ 1 ps) of the short time scale images (73 ps). We also determine that this method, using a reference laser pulse with a variable delay, leads to the determination of the time delay between the ionizing laser pulse and the reference pulse with an error of 0.6 ps (rms).

22 μW, 5.1 ps LSB, 5.5 ps RMS jitter Vernier time‐to‐digital converter in CMOS 65 nm for single photon avalanche diode array

A Vernier ring-oscillator-based time-to-digital converter (TDC) with a new prelogic is presented. Experimental results show that the proposed architecture achieve a 5.5 ps RMS timing jitter with a 5.1 ps LSB within an area of . Thanks to the new prelogic circuit, the power consumption of the circuit was optimised to at a rate of 1 Mevents/s for a dynamic range of 4 ns. The area, timing jitter and power consumption make the TDC suitable for an array of electronic readout in a position emission tomography single photon avalanche diode based detectors.

Near threshold voltage digital PLL using low voltage optimised blocks for AR display system

In this work, a digital phase-locked loop (DPLL) is proposed for the low power and stable operation in an augmented reality (AR) display system. The AR display system which needs the ultra-low power consumption adopts the near-threshold voltage (NTV) operation in both digital and analogue blocks. The NTV region has the advantage of small power dissipation with low-supply voltage. However, it suffers from performance degradation due to a large delay, slow transition time, and small dynamic voltage range. To achieve the optimised power efficiency and stable performance, the dynamic time-to-digital converter and the low voltage optimised digitally controlled oscillator are applied in the proposed DPLL. In addition, the forward body biasing scheme is used to increase the operation frequency for the sigma-delta modulator block. The proposed DPLL is fabricated using 65 nm CMOS technology and shows a current consumption of 160 μA at a voltage of 0.55 V. In addition, the jitter characteristic shows 6.7 ps rms jitter and 50 ps peak to peak jitter at 480 MHz.

CMOS integrated delay chain for X-Ku band applications

A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 $$\upmu \hbox {m}$$ CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from 8 to 18 GHz. The fabricated chip occupies an area of $$1.2\times 2.7$$ mm$$^{2}$$ and has no DC power consumption.

FPGA Implementation of a Synchronization Circuit for Arbitrary Trigger Sequences

In several applications, the generation/acquisition of data sequences is triggered by an external signal. Frame jitter, i.e., random temporal variations between the trigger signal and the actual start of data generation/acquisition, produces errors and inaccuracies. When, in a digital approach, the trigger is sampled by the internal clock of the receiving system, an uncertainty corresponding to the clock period (e.g., 10 ns for a 100-MHz clock) is produced. For several sensitive applications, like, for example, radar interferometry or ultrasound velocimetry, this uncertainty cannot be tolerated, making difficult the synchronization of external instrumentation or separated apparatuses. The problem is theoretically solved by sharing a common master clock among instruments, but not all the systems allow this solution. In this article, a full digital synchronization circuit is proposed, which measures the phase difference between the input trigger and the next edge of its internal clock and generates a copy of the clock with a phase tuned on the input trigger. This way, for every trigger pulse, the clock is rephased and the frame jitter is reduced. The circuit accepts nonperiodic triggers, making it suitable for a wider range of applications. Experiments with the proposed circuit implemented in a Field Programmable Gate Array (FPGA) are presented, which show a frame jitter reduction below 90 ps rms.

A high time resolution and low-power ASIC for MRPC applications

The structure of readout circuits needs to be improved to meet the requirements of the endcap time of flight upgrade with multi-gap resistive plate chamber (MRPC) in Beijing Spectrometer III experiments, posing a demand for the high time resolution and low-power electronics. Considering MRPC features, an application-specific integrated circuit (ASIC) called FEEWAVE, which integrates the front-end circuit and digitization function, is proposed to meet the above requirements. The front-end circuit implements I/V conversion and signal amplification. To reduce power consumption and further improve the time resolution, the waveform sampling technique based on switch capacitor array is adopted. A 30 fC to 1.2 pC input signal dynamic range is obtained, and the jitter is less than 21 ps rms. At the same time, the chip realizes 5 GSPS (gigabit samples per second) sampling rate, trigger rate capability of 50 kHz and 25 mW/channel power consumption. The 6-channel ASIC has been designed and taped out with 0.18 $$\upmu $$m complementary metal oxide semiconductor technology. The preliminary test results of FEEWAVE have been achieved.

A 256 Pixelated SPAD readout ASIC with in-Pixel TDC and embedded digital signal processing for uniformity and skew correction

Abstract Coincidence timing resolution (CTR) of 10 ps FWHM would drastically increase the contrast of images in pre-clinical and clinical positron emission tomography (PET) due to the capability to localize the annihilation site along the line of response with unprecedented accuracy. Currently, the scintillators and the photodetectors with their electronic readout are the two limiting factors to reach such a timing resolution. On the photodetector side, the single photon timing resolution (SPTR) must be improved below 4 ps RMS to reach a CTR of 10 ps FWHM. To this end, we propose to use a 3D digital silicon photomultiplier (3DdSiPM) where each single photon avalanche diode (SPAD) has its own quenching circuit (QC) and time-to-digital converter (TDC). To reach an SPTR of 4 ps RMS in an array of SPAD requires to correct each readout pixel individually to minimize the impact of TDC least significant bit (LSB) non-uniformities and SPAD-to-SPAD skew. For this purpose, we developed an array of 256 pixels of SPAD readout circuits optimized for high timing precision with embedded digital signal processing. The latter is a code-to-time conversion where each pixel is individually corrected for TDC LSB variation and skew. Measurement results on single pixels (QC and TDC) show timing jitter down to 8 ps RMS. The uncorrected array timing jitter is about 87 ps RMS and is reduced to 18 ps RMS after skew correction and TDC LSB correction.

12 Gbit/s three‐tap FFE half‐rate transmitter with low jitter clock buffering scheme

A 12 Gbit/s feed-forward equalisation (FFE) transmitter has been designed in 65 nm CMOS process. The three-tap/half-rate highspeed tap signal generation technique for the segmented FFE driver is presented. A clock buffer scheme to make the equivalent signal transition for each segmented unit contributes to a low jitter performance. The measurement results show 9.31 ps RMS jitter at 12 Gbit/s after equalisation and the horizontal eye-opening is 0.204 UI at 10 -12 BER. The prototype transmitter occupies 0.042 mm 2 and consumes 1.58 pJ/bit.

A Second-Order $\Delta\Sigma$ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits

In this brief, time-domain arithmetic circuits, such as time adder, time subtractor, and time integrator, are proposed. The concept of these time-domain circuits are explained and their non-idealities are analyzed. Using the proposed time-domain arithmetic circuits, a prototype second-order $\Delta \Sigma $ -time-to-digital converter is implemented in a 65 nm standard CMOS process. The fabricated chip achieves 1.44 ps rms of integrated noise in 1-MHz bandwidth while consuming 3.5 mW at 50 MS/s.

Investigating microchannel plate PMTs with TOFPET2 multichannel picosecond timing electronics

TOFPET2 is the second-generation design of a high-performance multichannel picosecond timing readout electronics ASIC produced by PETsys Electronics SA, Portugal. Originally developed for time-of-flight positron emission tomography using silicon photomultipliers, in this work we describe an experimental programme to evaluate the performance of TOFPET2 with pixelated microchannel plate (MCP) photomultiplier tube (PMT) detectors.Investigations were performed using various signal input methods; injected electronic stim signals, SiPM photodetectors, a single anode MCP photomultiplier detector and finally imaging with a demountable multi-anode MCP detector using a 16 x 16 pixelated multi-layer ceramic readout. The detector utilised an active anode plus image charge configuration to provide the positive signal pulses required by the electronics.Measurements were undertaken using the PETsys Time-of-Flight ASIC evaluation kit (mark2) operating in single photon counting mode. We present performance results for time resolution, cross channel coincidence time resolution and energy resolution using internal pulse amplitude measurement and time-over-threshold signal paths.Photodetector timing performance was evaluated using a 40 ps wide pulsed laser, operating at single photon level using a temperature stabilised setup within a dark enclosure. Amplitude walk correction was applied using the in-built time-over-threshold output from the TOFPET2 system. Single photon timing resolution of better than 110 FWHM was demonstrated. Preliminary results obtained using signal spread over adjacent pixels of a pixellated anode yield a coincidence timing resolution of ∼87 ps rms.

Implementation of 5.3 ps RMS precision and 350 M samples/second throughput time-to-digital converters with event sampling architecture in a Kintex-7 FPGA

Unlike the conventional field programmable gate array (FPGA) based time-to-digital converter (TDC) with clock sampling architecture, the TDC with event sampling architecture implemented in this paper propagates the system clock signal along the tapped-delay line (TDL) and the TDL status is sampled by a hit signal for time interpolation. Since there are several “1–0” and “0–1” transitions in the sampled TDL status, the TDC naturally realizes multiple measurements in parallel without increasing the resource consumption and the measurement dead time. Using a Xilinx Kintex-7 FPGA, we increase the number of equivalent TDC bins approximately to twice the number of physical delay cells in the TDL, which means the TDC resolution is about twice as good as the original. The average RMS precision is measured as 5.3 ps with two identical TDC channels measuring the time intervals in the range 0 to 20 ns. The proposed encoding scheme is so efficient that the TDC measurement throughput can reach 350 M samples per second. The test results show that the event sampling architecture is effective in FPGA as well. The performance that can be achieved is comparable with the performance of their counterparts that use the clock sampling architecture.

A monolithic ASIC demonstrator for the Thin Time-of-Flight PET scanner

Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a high-precision PET scanner for small animals. The chip uses a SiGe Bi-CMOS process for timing measurements, integrating a fully-depleted pixel matrix with a low-power BJT-based front-end per channel, integrated on the same 100 μm thick die. The target timing resolution of the scanner is 30 ps RMS for electrons from the conversion of 511 keV photons. The system will include 1.6 million channels across almost 2000 different chips. A full-featured demonstrator chip with a 3×10 matrix of 500×500 μm2 pixels was fabricated to validate each block. Its design and experimental results are presented here.

Digital instrument with configurable hardware and firmware for multi-channel time measures

A new digital instrument for timing of events is presented. It is based on a reconfigurable, high-performance, 16-channel time-to-digital converter implemented in a Xilinx 7 Series 28-nm field programmable gate array device. Each channel provides timestamps with a least significant bit of 2 ps that states the resolution, whereas instead the single-shot precision is below 12.5 ps rms with the possibility of multihit measures at the maximum rate of 20 MHz. The default width of the full-scale range is 157 µs that can be extended at users choosing up to 15 days by means of proper time tagging procedures made available. The instrument achieves performance in terms of precision, resolution, and full-scale range of measurement at the state-of-art of existing solutions. The novelty is that besides performance, the presented instrument is totally reconfigurable by the user both in the hardware and in the firmware parts. Moreover, novel techniques of event acquisition (e.g., level-zero trigger) are introduced. These further features are not present in any other instrument available nor in the literature or in commerce and constitute a difference with respect to all referenced instruments.

Operation of microchannel plate PMTs with TOFPET multichannel timing electronics

We describe an experimental programme to evaluate TOFPET multichannel timing electronics using microchannel plate PMTs in single photon counting mode. Time resolution measurements were made using: (i) the on-board electronic stim signal; (ii) a Photek PMT210 high speed single anode MCP photomultiplier detector, and; (iii) imaging with a PMT240MA multi-anode MCP detector using a pixelated multi-layer ceramic readout. Experimental measurements using an electronic stim with the ASIC electronics gave a time resolution of 43 ps rms. Detector timing of the PMT210 detector was evaluated using a 40 ps wide pulsed laser with amplitude walk correction using the time over threshold capability of the TOFPET electronics. Single photon timing resolution of better than 100 ps rms was demonstrated. Furthermore, 256 discrete pixel imaging has been demonstrated by coupling a multi-anode pixelated MCP detector to the TOFPET system. • First result for coupling TOFPET electronics to microchannel plate detectors. • 43 picosecond electronic time resolution measured. • Photon-counting with 96 picosecond time resolution. • 256 pixel ultra-fast microchannel plate imaging demonstrated. • Amplitude walk correction improves timing resolution from 225 to 96 picoseconds.

The Gigatracker detector of the NA62 experiment at CERN SPS

Abstract The NA62 experiment at the CERN SPS is a fixed target experiment designed to measure the branching ratio of the ultra-rare Kaon decay K + → π + ν ν . The experiment uses an high-momentum K + decay in-flight technique to increase the rejection power of the main background: K + → π + π 0 . The Gigatracker is a hybrid silicon pixel detector, exposed to a 750 MHz high-energy charged hadron beam, built to give an accurate measurement of K + momentum and direction together with an high precision measurement of the beam particle arrival time (115 ps RMS resolution per plane). It comprises three stations placed right before the K + decay region and inserted around two achromats. The detector works in vacuum ( ∼ 1 0 − 6 mbar ) at about − 10 ° C . Each station is made of a 200 μ m thick silicon sensor readout by 10 TDCPix, custom 100 μ m thick ASICs, and cooled by an innovative double circuit silicon micro-channel cooling system. All these parts are designed to minimize the total material budget which, in the final detector, amounts to less than 1.5% X 0 for the three stations. In order to sustain the high rate of incoming particles, each TDCPix, operating in a self triggered mode, is equipped with four 3.2 Gb/s serializers sending data to the detector DAQ system based on a read-out card per TDCPix chip sending trigger-matched hits to 6 PC servers. I will describe the whole detector and present some of the results from data collected during the 2016 NA62 runs.

A start to end simulation of the laser plasma wakefield acceleration experiment at ESCULAP

We present a start to end (s2e) simulation of the Laser-plasma Wakefield Accelerator (LPWA) foreseen as the ESCULAP project. We use a photo injector to produce a 5MeV 10pC electron bunch with a duration of ∼ 1 ps RMS, it is boosted to 10MeV by a S-band cavity and then compressed to 74 fs RMS (30 fs FWHM) by a magnetic compression chicane (dogleg). After the dogleg, a quadrupole doublet and a triplet are utilized to match the Twiss parameters before injecting into the subsequent plasma wakefield. A 40 TW laser is used to excite plasma wakefield in the 10 cm plasma cell. An optimized configuration has been determined yielding at the plasma exit an electron beam at 180 MeV with energy spread of ∼ 4.2%, an angular divergence of 0.6 mrad and a duration of 4 fs.

Highly Integrated FPGA-Only Signal Digitization Method Using Single-Ended Memory Interface Input Receivers for Time-of-Flight PET Detectors.

We propose a new highly integrated field-programm-able gate array (FPGA) only signal digitization method for individual signal digitization of time-of-flight positron emission tomography (TOF PET). We configured I/O port of the FPGA with a single-ended memory interface (SeMI) input receiver. The SeMI is a single-ended voltage-referenced interface that has a common reference voltage per I/O Bank, such that each SeMI input receiver can serve as a voltage comparator. The FPGA-only digitizer that uses the single-ended input receivers does not require a separate digitizing integrated chip, and can obtain twice as many signals as that using LVDS input receivers. We implemented a highly integrated digitizer consisting of 82 energy and 82 timing channels using a 28-nm FPGA. The energy and arrival time were measured using a 625-ps binary counter, and a 10-ps time-to-digital converter (TDC), respectively. We first measured the intrinsic characteristics of the proposed FPGA-only digitizer. The SeMI input receiver functioned as the voltage comparator without undesirable offset voltage. The standard deviation value of the time difference measured using two SeMI input receivers with respective TDCs was less than 14.6 ps RMS. In addition, we fed signals from the TOF PET detectors to the SeMI input receivers directly and collected data. The TOF PET detector consisted of a 3 × 3 × 20mm3 LYSO crystal coupled with a silicon photomultiplier. The energy resolutions were 7.7% and 7.1% for two TOF PET detectors. The coincidence resolving time was 204 ps full width at half maximum. The SeMI digitizer with a high-performance signal digitizer, processor, and high-speed transceivers provides a compact all-in-one data acquisition system.