Ps Rms Research Articles

Eight-Channel 21 ps Precision <inline-formula> <tex-math notation="LaTeX">$10~\mu \text{s}$ </tex-math></inline-formula> Range Time-to-Digital Converter Module

We present an eight-channel time-to-digital converter (TDC) instrument capable of measuring up to eight independent time intervals, with 21 ps rms precision and less than 1.5% LSB rms differential nonlinearity, over $10~\mu \text{s}$ full-scale range and up to 5.5 Mconv/s per channel. The module can also operate the eight channels in average or interleaved mode, i.e., as a single TDC, in order to improve timing performance or conversion rate, respectively. The on-board real-time data processing allows fast data transfer to a remote computer, through a Universal Serial Bus 2.0 interface, and a dedicated software interface handles measurements and plots data. Thanks to excellent timing performance and just 6 W power consumption, the eight-channel TDC module is suitable for advanced cost-effective multichannel time measurements at picosecond level.

A novel approach for pulse width measurements with a high precision (8 ps RMS) TDC in an FPGA

High precision time measurements are a crucial element in particle identification experiments, which likewise require pulse width information for Time-over-Threshold (ToT) measurements and charge measurements (correlated with pulse width). In almost all of the FPGA-based TDC applications, pulse width measurements are implemented using two of the TDC channels for leading and trailing edge time measurements individually. This method however, requires twice the number of resources. In this paper we present the latest precision improvements in the high precision TDC (8 ps RMS) developed before [1], as well as the novel way of measuring ToT using a single TDC channel, while still achieving high precision (as low as 11.7 ps RMS). The effect of voltage, generated by a DC-DC converter, over the precision is also discussed. Finally, the outcome of the temperature change over the pulse width measurement is shown and a correction method is suggested to limit the degradation.

A Wide Range, 4.2 ps(rms) Precision CMOS TDC With Cyclic Interpolators Based on Switched-Frequency Ring Oscillators

A time-to-digital (TDC) converter based on cyclic interpolators has been designed. The TDC is designed to be used in a pulsed time-of-flight laser radar, where a long measurement range is required. The TDC's two interpolators provide a picosecond level resolution, which is combined with a main reference clock counter to give a measurement range of 327 $\mu{\rm s}$ . The interpolators measure time intervals with a switched-frequency ring oscillator. The frequency switching is used as a mechanism to amplify the quantization error in the cyclic interpolator. A digital calibration scheme is used for radix extraction. The interpolators' worst case INL is $\pm$ 4.5 ps. Due to the interpolator's INL, the TDC's RMS precision is about 4.2 ps, while the worst and best case single-shot precisions are 5.5 ps and 1.7 ps, respectively. The overall accuracy of the TDC is better than 5 ps in a temperature range of $-$ 30 C to 70 C. The TDC is designed in 0.35 $\mu{\rm m}$ CMOS technology and consumes 80 mW at 0.8 MHz measurement rate.

A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS

This paper presents a power- and area-efficient multistandard serial link transceiver designed for backplane application rates of up to 28 Gb/s, such as OIF CEI-25G, CEI-28G, and IEEE 802.3bj 100G-KR4. The receiver features a continuous-time linear equalizer, variable gain amplifier, and a 14-tap decision feedback equalizer, including eight floating taps. The transmitter has a 2:1 multiplexer with a duty cycle distortion corrected half-rate clock and a full-rate source-series terminated driver with a 5-tap feed-forward equalizer. The shared PLL employs a transformer-based LC-VCO that achieves a VCO tuning range of 20G to 29 GHz and 0.23 ps RMS jitter at 28.125 GHz. The transmitter output shows only 50 fs duty-cycle distortion. The transceiver can compensate a 40 dB insertion loss backplane channel (excluding package) at a data rate of 25.78 Gb/s with eight channels running simultaneously. It is fabricated in 28 nm standard CMOS and analog section consumes only 295 mW at 1 V supply with transmitter driver at 1.25 V. Such low power consumption and performance are achieved by combination of advanced 28 nm process, low power and performance driven receiver and transmitter topologies, widely adopted bandwidth extension techniques, built-in analog calibrations and one common PLL with a transformer based VCO for four transceivers.

Time interval generator with 8 ps resolution and wide range for large TDC array characterization

Accurate generation of picosecond-resolution wide---range time intervals gives rise to a new time-efficient method for the characterization of large arrays of time-to-digital converters involved in time resolved imaging. This paper presents the design and measurement of a time interval generator based on FPGA technology. Although it can be employed in different automatic test setups, it has been designed to characterize an array of time-to-digital converters. It can work as periodic pulse/frequency generator but also as a digital-to-time converter. The accuracy of periodic pulse generator is around 20 ps RMS jitter for a pulse width ranging from 600 ps to 33 µs. The incremental time resolution is 8 ps and the repetition rate is up to 2 MHz. The accuracy of the digital-to-time converter is less than 0.8LSB DNL and 2LSB INL, whilst the time resolution is 27 ps. Full characterization of the module is reported including a comparison with state-of-the-art instruments in this field. The measurement results of the time-to-digital converter array driven by the designed digital-to-time converter module are presented as well. The effectiveness of the proposed method is evaluated by comparing it with the statistical code density test.

Waveform timing performance of a 5 GS/s fast pulse sampling module with DRS4**Supported by Knowledge Innovation Program of the Chinese Academy of Sciences (KJCX2-YW-N27), and National Natural Science Foundation of China (11175176)

We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. A calibration strategy is proposed, and as a result, the waveform timing performance is improved to below 10 ps RMS. We then further evaluate waveform-timing performance of the module by comparing with a 10 GS/s oscilloscope in a setup with plastic scintillators and fast PMTs. Different waveform timing algorithms are employed for analysis, and the module shows comparable timing performance with that of the oscilloscope.

An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation

This paper presents a low-power first-order frequency synthesizer architecture suitable for high-speed on-chip clock generation. The proposed design features an architecture combining an LC quadrature voltage-controlled oscillator (VCO), two sample-and-holds, a phase interpolator, digital coarse-tuning and rotational frequency detection for fine-tuning. Similar to multiplying delay-locked loops (MDLLs), this architecture limits jitter accumulation to one reference cycle, as jitter during one reference cycle does not contribute to the next reference cycles. Also, instead of using multiplexer switches commonly employed in MDLLs, the reference clock edge is injected by phase interpolation to support higher frequencies and lower jitter. Functionality of the frequency synthesizer is validated between 8-9.5 GHz, LC VCO's range of operation. First-order dynamic of the acquisition has been analyzed and demonstrated through measurement. The output clock at 8 GHz has an integrated rms jitter of 490 fs, peak-to-peak periodic jitter of 2.06 ps and total rms jitter of 680 fs. Different components of jitter have been analyzed and separate measurements have been done to support the analysis. The reference spurs are measured to be -64.3 dB below the carrier frequency. At 8 GHz the system consumes 2.49 mW from a 1 V supply.

Twenty Years of Rad-Hard K14 SPAD in Space Projects.

During last two decades, several photon counting detectors have been developed in our laboratory. One of the most promising detector coming from our group silicon K14 Single Photon Avalanche Diode (SPAD) is presented with its valuable features and space applications. Based on the control electronics, it can be operated in both gated and non-gated mode. Although it was designed for photon counting detection, it can be employed for multiphoton detection as well. With respect to control electronics employed, the timing jitter can be as low as 20 ps RMS. Detection efficiency is about 40 % in range of 500 nm to 800 nm. The detector including gating and quenching circuitry has outstanding timing stability. Due to its radiation resistivity, the diode withstands 100 krad gamma ray dose without parameters degradation. Single photon detectors based on K14 SPAD were used for planetary altimeter and atmospheric lidar in MARS92/96 and Mars Surveyor ’98 space projects, respectively. Recent space applications of K14 SPAD comprises LIDAR and mainly time transfer between ground stations and artificial satellites. These include Laser Time Transfer, Time Transfer by Laser Link, and European Laser Timing projects.

Experimental station for laser-based picosecond time-resolved x-ray absorption near-edge spectroscopy.

We present an experimental station designed for time-resolved X-ray Absorption Near-Edge Spectroscopy (XANES). It is based on ultrashort laser-plasma x-ray pulses generated from a table-top 100 mJ-class laser at 10 Hz repetition rate. A high transmission (10%-20%) x-ray beam line transport using polycapillary optics allows us to set the sample in an independent vacuum chamber, providing high flexibility over a wide spectral range from 0.5 up to 4 keV. Some XANES spectra are presented, demonstrating 1% noise level in only ∼1 mn and ∼100 cumulated laser shots. Time-resolved measurements are reported, indicating that the time resolution of the entire experimental station is 3.3 ± 0.6 ps rms.

A 1.7 ps Equivalent Bin Size and 4.2 ps RMS FPGA TDC Based on Multichain Measurements Averaging Method

A high precision and high resolution time-to-digital converter (TDC) based on multichain measurements averaging method is implemented in a 40 nm fabrication process Virtex-6 FPGA. The results of the detailed theoretical analysis and the simulation with the MATLAB tool based on a complete TDC module show that the resolution limitation determined by the intrinsic cell delay of plain tapped-delay chain can be overcame, which results in an improvement on both resolution and precision without increasing the dead time. The test results agree with the simulation results quite well. In such a TDC, the input signal is connected to multiple tapped-delay chains simultaneously (the number of the chains is M), and each chain is just a plain TDC and generates a timestamp for a hit signal. Therefore, M timestamps should be obtained in total, which, after averaging, give the final timestamp. A TDC with 1.7 ps equivalent bin size, 1.5 ps averaged bin size and 4.2 ps RMS has been implemented with M being 16, which performs much better than the plain TDC constructed of a single tapped delay chain having 42.3 ps equivalent bin size, 24.0 ps averaged bin size resolution and 13.2 ps RMS precision. The comparisons of equivalent bin size and averaged bin size show that the nonlinearity is improved with a larger M. Due to the real time integral nonlinearity (INL) calibration and averaging calculation, the multichain TDC is almost insensitive to the process voltage and temperature (PVT) variations.

Dual channel time‐to‐digital converter module with 10 ps resolution and 320 ns full scale range

A dual-channel time-to-digital converter (TDC) module designed to accurately measure time intervals with 10 ps resolution, about 21 ps root-mean-square (rms) precision and 125 fs rms differential nonlinearity, over a 320 ns full scale range and up to 4 Mconv/s per channel is presented. The module can also operate the two channels in parallel, as a single TDC converter, in order to improve timing performance to about 15.3 ps rms. A USB 2.0 interface provides the power supply and allows fast data transfer to a computer, where a dedicated software interface handles measurement data and plots. Because of the excellent timing performance, compact dimensions and low power consumption, the dual-channel TDC module is suitable for advanced multi-channel time measurements at the picosecond level.

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS

A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\bf mm}^{2}$</tex></formula> and 60 mW.

A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter

In this paper, a fourth-order ΔΣ time-to-digital converter (TDC) is proposed to achieve high resolution and wide signal bandwidth. The proposed TDC is based on a 1–3 multi-stage-noise-shaping (MASH) architecture, where the first-stage is a gated-ring oscillator based TDC (GRO-TDC) and the second-stage is a single-loop third-order ΔΣ TDC based on a time-domain error-feedback filter using time registers, time adders and time amplifiers. Implemented in 65 nm CMOS process, the prototype TDC achieves 0.22 ps rms of integrated noise within 15 MHz signal bandwidth at 300 MS/s while consuming lower than 6.24 mW. The proposed TDC occupies an active die area of only 0.03 mm 2 .

Low-jitter wide-range integrated time interval/delay generator based on combination of period counting and capacitor charging.

We present the design, operation, and test results of a new time interval/delay generator that provides the resolution of 0.3 ps, jitter below 10 ps (rms), and wide delay range of 10 s. The wide range has been achieved by counting periods of a reference clock while the high resolution and low jitter have been obtained through the two-time use of inner interpolation. This interpolation, based on charging of a single capacitor, provides both the precise external trigger synchronization and accurate generation of residual time interval. A combination of both processes virtually eliminates triggering indeterminacy. The jitter between the trigger and output is below 1 ps, which ensures a high performance delay. The generator is integrated in a single application specific integrated circuit chip using a standard cost-effective 0.35 μm CMOS process.

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.

Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs.

We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link.

A 10-Bit, 12 ps Resolution CMOS Time-to-Digital Converter Dedicated to Ultra-Fast Optical Timing Applications

This paper reports the design of a 10-bit, high-resolution time-to-digital converter (TDC) based on Vernier residues amplification which is a novelty. This TDC architecture allows the measurement of wide time intervals with high picosecond-range resolution. The key benefits of the proposed TDC are that it reduces conversion jitter and provides more design flexibility to enhance matching performances of delay cells and thus reach high conversion linearity regardless of the process technology, which is a strong aspect of the approach. Simulations results show that the TDC achieves a timing resolution of 12 ps rms in a long 12.5 ns timing window, a low core power consumption of 4.8 mW and estimated differential and integral nonlinearities (DNL and INL) of 0.73 and 2.02 LSB with a standard deviation of 0.17 and 0.94 LSB respectively. The TDC, implemented in 0.13 mm CMOS technology, occupies a total silicon area of 1.83 $$\times $$× 2.23 mm$$^2$$2 including pads. Such a TDC will find useful applications in tomographic systems, where several time-correlated single photon counting (TCSPC) channels need to be used in a massively parallel configuration such as in diffuse optical tomography or in time-of-flight positron emission tomography.

Design, conditioning, and performance of a high voltage, high brightness dc photoelectron gun with variable gap.

A new high voltage photoemission gun has been constructed at Cornell University which features a segmented insulator and a movable anode, allowing the cathode-anode gap to be adjusted. In this work, we describe the gun's overall mechanical and high voltage design, the surface preparation of components, as well as the clean construction methods. We present high voltage conditioning data using a 50 mm cathode-anode gap, in which the conditioning voltage exceeds 500 kV, as well as at smaller gaps. Finally, we present simulated emittance results obtained from a genetic optimization scheme using voltage values based on the conditioning data. These results indicate that for charges up to 100 pC, a 30 mm gap at 400 kV has equal or smaller 100% emittance than a 50 mm gap at 450 kV, and also a smaller core emittance, when placed as the source for the Cornell energy recovery linac photoinjector with bunch length constrained to be <3 ps rms. For 100 pC up to 0.5 nC charges, the 50 mm gap has larger core emittance than the 30 mm gap, but conversely smaller 100% emittance.

A new time calibration method for switched-capacitor-array-based waveform samplers

We have developed a new time calibration method for the DRS4 waveform sampler that enables us to precisely measure the non-uniform sampling interval inherent in the switched-capacitor cells of the DRS4. The method uses the proportionality between the differential amplitude and sampling interval of adjacent switched-capacitor cells responding to a sawtooth-shape pulse. In the experiment, a sawtooth-shape pulse with a 40ns period generated by a Tektronix AWG7102 is fed to a DRS4 evaluation board for calibrating the sampling intervals of all 1024 cells individually. The electronic time resolution of the DRS4 evaluation board with the new time calibration is measured to be ~2.4ps RMS by using two simultaneous Gaussian pulses with 2.35ns full-width at half-maximum and applying a Gaussian fit. The time resolution dependencies on the time difference with the new time calibration are measured and compared to results obtained by another method. The new method could be applicable for other switched-capacitor-array technology-based waveform samplers for precise time calibration.

A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function

A 9.2 GHz digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer function is presented. In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast settling without exhibiting overshoots. While most previously reported peaking-free PLLs require additional circuit components which may adversely affect clock jitter or increase hardware complexity, the presented PLL requires only a new type of digital loop filter. The analysis on the loop dynamics and design of the optimal loop filter are presented. As for the implementation, a low-power linear time-to-digital converter (TDC) is realized with a set of three binary phase-frequency detectors whose triggering clocks are dithered using a delta-sigma modulator and phase interpolators. A digitally controlled oscillator (DCO) is implemented as a transformer-tuned LC oscillator whose frequency is set by a ratio between two digitally controlled currents. The digital PLL prototype, fabricated in a 65 nm CMOS, demonstrates 1.2 ps rms integrated jitter at 9.2 GHz and 1.58 μs settling time with 700 kHz bandwidth while dissipating 63.9 mW at a 1.2 V nominal supply.