Ps Rms Research Articles

Wafer-Level Vacuum-Packaged High-Performance AlN-on-SOI Piezoelectric Resonator for Sub-100-MHz Oscillator Applications

A high quality factor ( $Q$ ) and low-impedance aluminum nitride (AIN) on silicon piezoelectric resonator is reported in this paper. The piezoelectric resonator is fabricated based on the AIN-on-cavity-Silicon-on-Insulator (SOI) platform and vacuum encapsulated using the wafer-level chip-scale packaging by aluminum–germanium eutectic bonding approach. The fabricated resonator achieves a loaded $Q$ of 9520 and a motional impedance of 32.64 $\Omega$ at its series resonant frequency of 27.19 MHz. Thermal cycles (TC) and highly-accelerated stress test (HAST) are performed to evaluated the packaging reliability of the fabricated devices. No obvious impedance change caused by the TC and HAST is observed. The TC results indicate that the packaged devices have an equivalent life of more than 11.65 years based on the Coffin–Manson model. The piezoelectric resonator-based programmable oscillators demonstrate an overall frequency drift of $\pm$ 3 ppm over the temperature range of $-$ 20 $^{\circ }$ C to 70 $^{\circ }$ C thanks to the passive and active temperature compensations. With this stable frequency reference, the programmable oscillator produces a 75.01-MHz frequency output. The measured integrated phase jitter is 2.02 ps (rms) from 12 to 10 MHz.

A 5 pJ/pulse at 1-Gpps Pulsed Transmitter Based on Asynchronous Logic Master–Slave PLL Synthesis

This paper presents an ultralow power asynchronous logic transmitter operating at 1 Gpps that achieves pulse synthesis using a double phase-locked loop (PLL) architecture for applications exploiting large-scale neuronal interfacing with CMOS probes. The 4 GHz center frequency OOK transmitter synthesizes 500 ps duration pulses from a 31.25 MHz crystal oscillator using a cascade of a master and a slave PLL with the latter locked to the former. Both PLLs are implemented with CMOS digital cells and ring oscillator-based VCO. A prototype fabricated in a 130 nm RFCMOS process operates at a measured 5 pJ/pulse energy budget for an active area of 0.04 mm2. To generate timing references and packets for high data rate recording devices, the synthesizer core feeds also a logic interface operating at 250 MHz with four 1.2–3.3 V external parallel channels. From reset time, the master–slave PLL combination achieves locking in a measured time of 450 ns, settling is resolved in $\sim 4~\mu \text{s}$ , and the output pulses across the antenna load are generated with a 3.42 ps RMS jitter standard deviation. The obtained phase noise of a continuous OOK stream at 1 and 4 GHz, 1 MHz offset, is −103 and −93 dBc/Hz, respectively.

Prototype of a transient waveform recording ASIC

The paper presents the design and measurement results of a transient waveform recording ASIC based on the Switched Capacitor Array (SCA) architecture. This 0.18 μm CMOS prototype device contains two channels and each channel employs a SCA of 128 samples deep, a 12-bit Wilkinson ADC and a serial data readout. A series of tests have been conducted and the results indicate that: a full 1 V signal voltage range is available, the input analog bandwidth is approximately 450 MHz and the sampling speed is adjustable from 0.076 to 3.2 Gsps (Gigabit Samples Per Second). For precision waveform timing extraction, careful calibration of timing intervals between samples is conducted to improve the timing resolution of such chips, and the timing precision of this ASIC is proved to be better than 15 ps RMS.

A large area diamond-based beam tagging hodoscope for ion therapy monitoring

The MoniDiam project is part of the French national collaboration CLaRyS (Contrôle en Ligne de l’hAdronthérapie par RaYonnements Secondaires) for on-line monitoring of hadron therapy. It relies on the imaging of nuclear reaction products that is related to the ion range. The goal here is to provide large area beam detectors with a high detection efficiency for carbon or proton beams giving time and position measurement at 100 MHz count rates (beam tagging hodoscope). High radiation hardness and intrinsic electronic properties make diamonds reliable and very fast detectors with a good signal to noise ratio. Commercial Chemical Vapor Deposited (CVD) poly-crystalline, heteroepitaxial and monocrystalline diamonds were studied. Their applicability as a particle detector was investigated using α and β radioactive sources, 95 MeV/u carbon ion beams at GANIL and 8.5 keV X-ray photon bunches from ESRF. This facility offers the unique capability of providing a focused (~1 μm) beam in bunches of 100 ps duration, with an almost uniform energy deposition in the irradiated detector volume, therefore mimicking the interaction of single ions. A signal rise time resolution ranging from 20 to 90 ps rms and an energy resolution of 7 to 9% were measured using diamonds with aluminum disk shaped surface metallization. This enabled us to conclude that polycrystalline CVD diamond detectors are good candidates for our beam tagging hodoscope development. Recently, double-side stripped metallized diamonds were tested using the XBIC (X Rays Beam Induced Current) set-up of the ID21 beamline at ESRF which permits us to evaluate the capability of diamond to be used as position sensitive detector. The final detector will consist in a mosaic arrangement of double-side stripped diamond sensors read out by a dedicated fast-integrated electronics of several hundreds of channels.

Longitudinal compression and transverse matching of electron bunch for external injection LPWA at ESCULAP

We present theoretical and numerical studies of longitudinal compression and transverse matching of electron bunch before injecting into the Laser–plasma Wake Field Accelerator (LWFA) foreseen at the ESCULAP project in ORSAY. Longitudinal compression is performed with a dogleg chicane, the chicane is designed based on theory of beam optics, beam dynamics in dogleg is studied with ImpactT (Martin Dohlus and Torsten Limberg, 2004) and cross checked with CSRtrack (Qiang and Steve Lidia, 2006), both 3D space charge (SC) and coherent synchrotron radiation (CSR) effects are included. Simulation results show that the energy chirp at the dogleg entrance should be smaller than the nominal optic design value, in order to compensate the negative energy chirp increase caused by longitudinal SC, while CSR can be ignored in our case. With an optimized configuration, the electron bunch (∼10 MeV, 10 pC) is compressed from 0.9 ps RMS to 70 fs RMS (53 fs FWHM), with a peak current of 152 A. Transverse matching is realized with a doublet and a triplet, they are matched with Madx and the electron bunch is tracked with ImpactT, simulation results show little difference with the nominal design values, that is due to the SC effect. Finally, by simply adjusting the quadrupole strength, a preliminary optimized configuration has been achieved, that matches the Courant–Snyder (C–S) parameters to αx=0.01,αy=−0.02,βx=0.014m,βy=0.012m at the plasma entrance.

Low‐jitter spread spectrum clock generator using charge pump frequency detector in 0.18 μm CMOS for USB3.1 transceivers

This study presents a spread spectrum clock generator (SSCG) circuit for high-speed applications. The proposed SSCG adopts a phased locked loop with two dual voltage-controlled oscillators and a frequency modulation loop implemented with a novel control unit to achieve the desired spectrum-spreading profile. The control unit consists of an analogue charge pump-based frequency comparator that can determine the deviation of spread spectrum clock frequency from the reference frequency. Using this analogue frequency comparator simplifies the SSCG control unit and mitigates the design constraints, particularly the speed requirements of SSCG control unit. Hence, the structure becomes a suitable solution for high-speed applications. The proposed SSCG is tailored for USB3.1 standard with −4000 to −5000 ppm down spreading at 5 GHz clock frequency and 30–33 kHz modulation frequencies. The circuit is designed in TSMC 0.18 μm 1P6M CMOS process that occupies 0.13 mm2 active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non-spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with −5000 ppm down spread. The simulation results of the proposed system are compared with recent works.

A Sierpinski Space-Filling Clock Tree Using Multiply-by-3 Fractal-Coupled Ring Oscillators

A space-filling clock tree is presented, which takes an advantage of LC resonant clocking, to obtain a uniform phase and amplitude multiply-by-3 clock from a unique Sierpinski-coupled ring oscillator (SCRO) array. The three-stage interleaved SCROs resemble the Sierpinski triangle, and are synchronized with a common frequency to all. The SCRO further provides an aligned output phase relationship to reduce skew. The triangle clock grid with a side length of 3.2 mm is filled by a space-filling clock tree. The 3-D stacked transformers at the tree endpoints extract the third harmonic of the SCRO array oscillation and scale the voltage amplitude of the extracted clock. The transformers also perform a built-in bandpass filtering function to remove injected noise. An experimental prototype integrated in a 90-nm CMOS operates at 2.85–4.3 GHz and consumes 19.2–49 mW under 0.7–1 V supply voltages. With 300-mV added supply noise, jitter was measured as 3.4 ps (rms) and 17.7 ps (pp). The measured results reveal substantial improvements in both power and jitter from this approach.

Low Power and Small Area, 6.9 ps RMS Time-to-Digital Converter for 3-D Digital SiPM

Time-of-flight measurements are becoming essential to the advancement of several fields, such as preclinical positron emission tomography and high energy physics. Recent developments in single photon avalanche diode (SPAD)-based detectors have spawned a great interest in digital silicon photomultipliers (dSiPMs). To overcome the tradeoff between the photosensitive area and the processing capabilities in current 2-D dSiPM, we propose a novel 3-D digital SiPM, where the SPAD, designed for maximal photosensitive area, will be stacked in 3-D over the electronic circuits, designed in a CMOS node technology. All readout circuits will be implemented directly under the SPAD real estate, including quenching circuit, time-to-digital converter (TDC) and digital readout electronics. This paper focusses on the TDC element of this system, designed in TSMC CMOS 65 nm. This ring oscillator-based Vernier TDC requires only 25 $ {\times }$ 50 $ {\mu }\text{m}^{2}$ and 160 $ {\mu }\text{W}$ , and achieves 6.9 ps rms timing accuracy.

Unified Communication Framework

The unified communication framework (UCF) is a unified network protocol and field programmable gate array core for high-speed serial interfaces employed in data acquisition systems. It provides up to 64 different communication channels via a single serial link. One channel is reserved for timing and trigger information, whereas the other channels can be used for slow control interfaces and data transmission. All channels except the timing are bidirectional and share network bandwidth according to assigned priority. The timing channel distributes messages with fixed and deterministic latency in one direction. In this regard, the protocol implementation is asymmetric. The precision of the timing channel is given by the jitter of the recovered clock and is typically in the order of 10–20 ps rms. The timing channel has highest priority and a slow control interface should use the second highest priority channel in order to avoid long delays due to high traffic on other channels. The framework supports point-to-point connections and starlike 1:n topologies for optical networks with a passive splitter. It always employs one of the connection parties as a master and the others as slaves. The starlike topology can be used for front ends with low data rates or pure time distribution systems. In this case, the master broadcasts information according to assigned priority, whereas the slaves communicate in a time sharing manner to the master. In the open systems interconnection layer model, the UCF can be classified as layers one to three, which includes the physical, the data, and the network layer.

Multichannel FPGA based MVT system for high precision time (20 ps RMS) and charge measurement

In this article it is presented an FPGA based Multi-Voltage Threshold (MVT) system which allows of sampling fast signals (1–2 ns rising and falling edge) in both voltage and time domain. It is possible to achieve a precision of time measurement of 20 ps RMS and reconstruct charge of signals, using a simple approach, with deviation from real value smaller than 10%. Utilization of the differential inputs of an FPGA chip as comparators together with an implementation of a TDC inside an FPGA allowed us to achieve a compact multi-channel system characterized by low power consumption and low production costs. This paper describes realization and functioning of the system comprising 192-channel TDC board and a four mezzanine cards which split incoming signals and discriminate them. The boards have been used to validate a newly developed Time-of-Flight Positron Emission Tomography system based on plastic scintillators. The achieved full system time resolution of σ(TOF) ≈ 68 ps is by factor of two better with respect to the current TOF-PET systems.

Prototype of the Readout Electronics for WCDA in LHAASO

In the Large High Altitude Air Shower Observatory (LHAASO), the Water Cherenkov Detector Array (WCDA) is one of the key parts. The WCDA consists of 3600 Photomultiplier Tubes (PMTs) scattered in a 90000 m2 area, and both high precision time and charge measurements are required over a large dynamic range from 1 to 4000 Photo Electrons (P.E.). To achieve time measurement precision better than 500 ps RMS, high quality clock distribution and automatic phase compensation are needed among the 400 Front End Electronics (FEE) modules. To simplify the readout electronics architecture, clock, data, and commands are transferred simultaneously over 400-meter fibers, while high speed data transfer interface is implemented based on TCP/IP protocol. Design and testing of the readout electronics prototype for WCDA is presented in this paper. Test results indicate that a charge resolution better than 10% RMS @ 1 P.E. and 1% RMS @ 4000 P.E., and a time resolution better than 300 ps RMS are successfully achieved over the whole dynamic range, beyond the application requirement.

Portable Calibration Node for LHAASO-KM2A Detector Array

Aiming to high sensitivity and wide spectrum of cosmic ray detection, the 1 km2 complex array of large high altitude air shower observatory (LHAASO-KM2A) project consists of over 7000 detectors of different types. To reconstruct the air shower events with high angular resolution, timestamps of all detector electronics and digitizers should be aligned better than 500 ps RMS. White Rabbit (WR) technology, a fully deterministic Ethernet-based network with subnanosecond synchronization accuracy and picoseconds precision, is applied to build the dedicated data and timing network. To guarantee the overall synchronization precision, individual calibration of each WR node is essential to compensate device deviation. This paper talks about autocalibration procedure of all nodes in the LHAASO-KM2A WR network using the portable calibration node (PCN). Usage of the PCN in deploying the detectors array and validating synchronization performance of the WR network is also discussed.

Picosecond precision time‐of‐flight digital converter

Time-of-flight (TOF) digital converter implemented in field programmable gate array has been introduced. The operation is based on train of pulses transmission and counting received pulses in bank of counters. The bank of counters clock signal and the transmitted pulses clock signal are slightly different in frequency. This small difference is a key factor for the measurement method and is achieved by phase locked loop. TOF for the transmitted pulses is directly calculated upon counters counts. Time interval resolution for the prototype instrument is 10.4 ps and average RMS uncertainty value is 12.3 ps. There is no need for special calibration. TOF digital converter requires minimum amount of resources and is suitable for low-cost applications.

Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays

CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

A Novel Time-to-Digital Converter Based on Low-Jitter Phase-Locked Loop

ABSTRACTThis paper presents a novel multi-levels time-to-digital converter (TDC) suitable for array architecture for the photon time-of-flight (TOF) measurement. A simple method was applied to solve the initial phase time mismatch caused by random occurrence of the TOF start signal. A low-jitter phase-locked loop (PLL) is adopted to provide excellent clocks to the TDC. The proposed PLL–TDC has a good differential nonlinearity (DNL) (±0.4 LSB) and integral nonlinearity (INL) (±0.5 LSB) due to the low-jitter clock and elimination of initial phase time mismatch. The circuit of the low-jitter PLL was implemented in TSMC 0.35 µm standard complementary metal oxide semiconductor (CMOS) process with 3.3 V supply voltage. The measured result of the low-jitter PLL and the simulated result of the TDC show the proposed 14-bit TDC can realize 1.0 ns time resolution and 16 µs maximum range with 125 MHz centre frequency. Under this given frequency, the time interval error (TIE) jitter is 7.8 ps(rms).

A 0.5–9.5-GHz, 1.2- $\mu \text{s}$ Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling

A phase-locked loop (PLL) architecture is proposed for improved efficiency of power and thermal management techniques in system-on-chips (SoCs). PLL architecture introduces two techniques: a dual-stage phase-acquisition loop filter that enables fast lock time of 1.2 $\mu \text{s}$ without any frequency overshoots and a nonlinear DCO that enables a wide frequency range of 0.5–9.5 GHz and a low period jitter of ±1.25%UI p-p with a single wideband tuning. With this proposed PLL architecture, SoC can continue its operation without any interruption caused by frequency overshoots during power and thermal management techniques like dynamic core-count scaling and dynamic voltage frequency scaling. The PLL achieves 0.45 ps rms period jitter at 3.25 GHz in fractional-N mode operation, while consuming a total power of 7.1 mW.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9ps time-interval RMS precision, 16 TDC channels with 6.9ps RMS precision, or 8 TDC channels with 5.8ps RMS precision. All TDCs have a 380M Samples/second measurement throughput and a 2.63ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

Research of time discrimination circuits for PMT signal readout over large dynamic range in LHAASO WCDA

In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO), both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. for the PMT signal readout. In this paper, we present our work on the design of time discrimination circuits in LHAASO WCDA, especially on improvement to reduce the circuit dead time. Several approaches were studied through analysis and simulations, and actual circuits were designed and tested in the laboratory to evaluate the performance. Test results indicate that a time resolution better than 500 ps RMS is achieved in the whole large dynamic range, and the circuit dead time is successfully reduced to less than 200 ns.

Project on the superposition of beamlines for parametric X-ray radiation and coherent transition radiation in the THz region at LEBRA

A new project to develop a terahertz (THz)-wave light source is in progress at the parametric X-ray (PXR) beamline of the Laboratory for Electron Beam Research and Application (LEBRA) at Nihon University. The THz-wave source is based on coherent transition radiation (CTR) emitted from a metal foil inserted downstream from a crystal target that is the PXR radiator. Beryllium or titanium foil is the most promising candidate for a THz-wave radiator. Since the electron linac of LEBRA was developed for a free electron laser (FEL), electron beam with bunch length of 1 ps (rms) can be provided by magnetic bunching at the bending magnet section. Thus, very intense coherent transition radiation (CTR) can be obtained in the frequency region around 1 THz. The results of preliminary experiments for CTR production suggested that sufficiently intense THz-CTR can be obtained using the LEBRA linac. In order to realize a THz-wave source for practical application studies, we have a plan to add the extraction feature for THz waves to the PXR beamline.

A 0.0054-mm2Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor

In this brief, a frequency-to-current conversion-based fractional frequency synthesizer is implemented in 32-nm technology utilizing a high-density deep trench capacitor. The technique proposed here can replace the use of multiple crystal oscillators or a phase-locked loop for medium accuracy clock generation with very low chip area and power consumption. In addition to exploiting the inherently low variation of capacitors as compared to that of transistors, the proposed circuit generates an output frequency proportional to the capacitor ratio, canceling out any small process-voltage-temperature (PVT) dependences of the capacitor. The performance of the fractional synthesizer is verified from chip measurement results. An output frequency range of 16–156 MHz is covered with a frequency resolution of 0.8 MHz using a 4-MHz reference clock. The total area of the frequency synthesizer core is only 0.0054 mm2, and it consumes 116 $\mu\mbox{W}$ of power from a 0.9-V supply while generating an output frequency of 48 MHz. The output frequency variation is ±0.14% at 48 MHz for a temperature sweep from −40 °C to 90 °C. Periodic jitter measured from an on-chip high-resolution jitter measurement circuit is 115 ps (rms) at 76 MHz.