Proximity Correction Techniques Research Articles

The study of lithographic variation in resistive random access memory

Reducing the process variation is a significant concern for resistive random access memory (RRAM). Due to its ultra-high integration density, RRAM arrays are prone to lithographic variation during the lithography process, introducing electrical variation among different RRAM devices. In this work, an optical physical verification methodology for the RRAM array is developed, and the effects of different layout parameters on important electrical characteristics are systematically investigated. The results indicate that the RRAM devices can be categorized into three clusters according to their locations and lithography environments. The read resistance is more sensitive to the locations in the array (~30%) than SET/RESET voltage (<10%). The increase in the RRAM device length and the application of the optical proximity correction technique can help to reduce the variation to less than 10%, whereas it reduces RRAM read resistance by 4×, resulting in a higher power and area consumption. As such, we provide design guidelines to minimize the electrical variation of RRAM arrays due to the lithography process.

Machine Learning based Optical Proximity Correction Techniques

Machine Learning based Optical Proximity Correction Techniques

Electron beam lithography on curved or tilted surfaces: Simulations and experiments

There is a growing interest for patterning on curved or tilted surfaces using electron beam lithography. Computational proximity correction techniques are well established for flat surfaces and perpendicular exposure, but for curved and tilted surfaces adjustments are needed as the dose distribution is no longer cylindrically symmetric with respect to the surface normal. A graphical processing unit -accelerated 3D Monte Carlo simulation, based on first-principle scattering models, is used to simulate the asymmetric dose distribution. Based on that, an approximate adjustment is made to an existing high-performance proximity effect correction (PEC) algorithm aimed at the correct exposure of a pattern of nanowires on a 17° tilted surface. It was experimentally verified that using the adjusted PEC indeed leads to a more uniform exposure on tilted surfaces.

Optical proximity correction for a versatile LCD based direct write maskless photoplotter

The digital simulation of a photoplotter’s direct write process, where the reconfigurable mask is a liquid crystal microdisplay, leads to the development of two proximity correction techniques. The first works by modifying dimensions and in adding serifs or assistant features to the original structure design. The second, more innovative and only exploitable with a grey level capable direct writing device, precompensates structures with a multilevel spatial modulation of the luminous energy. We also present the computer simulation used to develop these OPC techniques and confirm its performance by comparing modelled and experimental results.

Tricks of the light [optical lithography

Physical IC design keeps getting more difficult as efforts to extend optical lithography beyond the 65nm generation impose limits on layouts. Process engineers have decided that they are stuck with the type of ultraviolet light that they use today in chipmaking for at least the next couple of generations of chip technology. The 193nm wavelength appeared with the 90nm process just as research on 157nm wound up because of problems with lenses and resists. That means the wavelength of light used to draw features on a chip is several times larger than the features themselves. As minimum process dimensions have shrunk to even smaller fractions of the illumination wavelength, various post-layout optimizations have been introduced to compensate for diffraction effects that result. Optical proximity correction techniques ensure that very closely spaced layout features can be formed on the wafer, by taking account of the way that light patterning one feature interferes with light patterning its neighbor. These corrections have been joined by other resolution enhancement techniques that continue to put pressure on designers to conform to increasingly complicated rules. At the same time, the techniques make the relationship between the original layout and what appears on the wafer less certain.

Shape engineering: A novel optical proximity correction technique for attenuated phase-shift mask

Modifications of the shapes and relative orientations of contact windows in attenuated phase shifting mask are studied theoretically and experimentally to maximize process latitude and resolution and to minimize sidelobe printability. By utilizing a non-square contact window shape and maintaining the overall pattern transmission, we achieve considerable sidelobe suppression with no loss in process latitude and resolution.

Challenges for 0.35-0.25 μm optical lithography

Lithography has enabled the continuous shrinking of device geometry over many years. Whereas it has been predicted many times that optical lithography would run out of steam, it still is the technology of choice, and this will certainly remain for a considerable time. Traditionally, this scaling has been made possible by using lower wavelength light sources and higher numerical aperture projection lenses. It is generally believed that i-line will be the mainstream technology for 0.35 μm lithography, while DUV (248 nm) will be needed for 0.25 μm. During the last years, various resolution enhancement techniques, such as phase shifting masks, off-axis illumination and surface imaging have been proposed. Very often, these techniques have been optimized to reduce the depth-of-focus loss, which is unavoidable using the lower wavelengths and higher numerical apertures. In this paper the current challenges for printing 0.35-0.25 μm dimensions will be reviewed. Although the mainstream technologies for 0.35 and 0.25 μm are more or less settled, the main challenge will most likely be critical dimension (CD) control. Optical proximity effects and substrate reflections start to play a major role in the CD budget. Methods to overcome these problems are obviously optical proximity correction techniques and the use of anti-reflective coatings and surface imaging. Moreover, a lot of gain can be obtained from reoptimizing current processes for maximum exposure latitude, combined with the minimally required focus budget. It will be shown that optimization of the lithography process (stepper parameters, mask, illumination, resist process) towards CD control results in different conclusions than optimization towards maximum depth-of-focus (DOF). Furthermore, a practical example of 0.25 μm lithography, using the combination of attenuated PSM and off-axis illumination, will be given. In an attempt to indicate the future of optical lithography, a simulation study is presented which starts from this example. Reasonable processing windows are obtained down to 0.12 μm by using ‘known’ techniques.

GHOST proximity correction technique: Its parameters, limitations, and process latitude

The efficacy of the GHOST proximity correction technique for achieving submicron linewidth control in electron beam lithography has been experimentally evaluated. Using the AT&T electron beam exposure systems, the GHOST parameters (correction dose, defocused beam diameter, and overlay accuracy) required for proximity exposure correction at 20 kV were determined via scanning electron microscopy and electrical linewidth measurement techniques. Optimum proximity correction conditions were established from a matrix of correction doses and correction beam diameters on two different substrates: chromium on glass and aluminum on silicon. On chromium, linewidth control of better than ±0.05 μm was obtained using a 3‐μm beam and a correction dose between 30% and 40% of incident, or with a 4‐μm beam and a 40% correction dose. Even better proximity correction was achieved on aluminum with a 5‐μm defocused beam and a 30% correction dose. In conjunction with the experimental data, a computer model was developed to inte...

Variable-shaped electron-beam direct writing technology for 1-µm VLSI fabrication

A 1-µm 256K MOS RAM has been fabricated using a variable-shaped electron-beam (EB) direct writing technology. EB drawing data are prepared using a new program, PEBL, which includes a new algorithm for shot division. PEBL plays an important role in obtaining high EB system throughput and high quality patterns. A new proximity correction technique, DCA, has also been proposed. This technique is simple and very effective in fabricating 1-µm VLSI patterns. Negative resist CMS or positive resist FPM are used appropriately, according to process levels. In fabrication of a 1-µm 256K MOS RAM, ±0.2-µm overlay accuracy and ±0.1-µm linewidth accuracy were achieved.

Proximity Correction Enhancements for 1-µm Dense Circuits

The proximity effect in electron-beam lithography, which is due to electron scattering in the resist and wafer, results in nonuniform exposure and development for patterns in which the incident doses of all the shapes are the same. Correction for this effect has been accomplished in the past primarily by varying the incident doses of all the shapes in order to achieve an equal average resultant dose per unit area for all shapes. We show that in the case of dense circuits with linewidths of about 1 µm or smaller, two enhancements to the proximity correction technique can be easily implemented. One of these is a simple approach to shape breakup (partitioning) to enable dose correction to be applied nonuniformly within the original design shapes. The other technique is a new type of algorithm for forming subsets of the design to perform self-consistent dose correction. These two enhancements are applied to LSI chip data for dense circuits and are shown to permit fabrication of circuits which would be more difficult to process using the proximity correction techniques described previously, due to the particular geometries present in these circuit designs. We also show the application of step and repeat pattern recognition algorithms to compact the resulting data, and consequently to reduce the amount of data by an amount which is greater than the increase in the number of shapes caused by partitioning.