Abstract

Physical IC design keeps getting more difficult as efforts to extend optical lithography beyond the 65nm generation impose limits on layouts. Process engineers have decided that they are stuck with the type of ultraviolet light that they use today in chipmaking for at least the next couple of generations of chip technology. The 193nm wavelength appeared with the 90nm process just as research on 157nm wound up because of problems with lenses and resists. That means the wavelength of light used to draw features on a chip is several times larger than the features themselves. As minimum process dimensions have shrunk to even smaller fractions of the illumination wavelength, various post-layout optimizations have been introduced to compensate for diffraction effects that result. Optical proximity correction techniques ensure that very closely spaced layout features can be formed on the wafer, by taking account of the way that light patterning one feature interferes with light patterning its neighbor. These corrections have been joined by other resolution enhancement techniques that continue to put pressure on designers to conform to increasingly complicated rules. At the same time, the techniques make the relationship between the original layout and what appears on the wafer less certain.

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