Proposed SAR ADC Research Articles

A Non-Linear Successive Approximation Finite State Machine for ADCs with Robust Performance

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications.

A 12-Bit SAR ADC with Binary Search Calibration Algorithm for a Split Capacitor

This paper proposes a 12-bit SAR ADC capable of calibrating a split capacitor using a binary search technique for bio-signal processing applications. The proposed SAR ADC employs a calibration logic circuit to calibrate a split capacitor vulnerable to process variations and mismatches. The proposed foreground calibration process involves four iterations through the binary search algorithm. In this manner, the calibration speed can be increased by up to 3.75 times compared with that of the linear search calibration. The proposed SAR ADC was implemented with a CMOS 28 nm 1-poly 8-metal process. The effective layout, excluding bonding pads, occupied 939 × 450 μm. Measurement results illustrated a power consumption of 30.7 μW (analog power: 16.1 μW and digital power: 14.6 μW), INL/DNL of −1.8/1.7 LSB, and −0.7/0.7 LSB, respectively, ENoB of 10.3-bit, and a FoM of 53.7 fJ/step.

A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications.

A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage Vaq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s.

A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient Switching Scheme for Wearable Biosensor Applications.

A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage Vcm, and common-mode techniques, the proposed switching scheme achieves 93.76% less switching energy compared to the conventional scheme with common-mode voltage shift in one LSB. With the switching scheme, the proposed SAR ADC can lower the dependency on the accuracy of Vcm and the complexity of digital control logic and DAC driver circuits. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low sampling error sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrate that the ADC achieves a 61.77 dB SNDR and a 78.06 dB SFDR and consumes 4.45 μW of power in a 180 nm process with a 1 V power supply, a full-swing input signal frequency of 93.33 kHz, and a sampling rate of 200 kS/s.

A 93.4-dB SNDR single-ended SAR ADC with a hybrid R–C DAC

In highly-integrated automatic test equipment (ATE) systems, the quantization process of single-ended analog signals demands high-precision ADCs. This paper presents a high precision single-ended SAR ADC with a hybrid R–C DAC. The proposed SAR ADC is demonstrated through sequential modeling in MATLAB, pre-layout and post-layout simulation. Designed in 0.18 μm BCD process, the post-layout simulation results show that it achieves a peak SNDR of 93.4-dB, a peak SFDR of 98.6-dB with a 250 kHz bandwidth. The power consumption of this SAR ADC is 5.96 mW with 5V supply. The Schreier Figure-of Merit (FoMSNDR) is 169.6-dB. The presented ADC is suitable for low-speed, high-precision ATE systems.

A 14-bit 1.2-V low power SAR ADC with digital background calibration in 0.18 μm CMOS

A 14-bit successive-approximation-register analog-to-digital converter is proposed for intelligent sensing application. A redundant integer sub-radix-2 capacitor array is adopted to recover the conversion errors. The capacitor mismatch is further mitigated with the digital background calibration. Different from the previous calibration that requires two ADC channels, the calibration approach is based on a single ADC, resulting in a considerable area reduction. The input signal injected with two different values are successively quantized twice by this ADC, and then digital background calibration is performed with these two output data. Designed with a 0.18 μm CMOS technology, the proposed SAR ADC occupies an area of 0.5682 mm2. The design results indicate that the SAR ADC can achieve a signal-to-noise distortion ratio of 77.6 dB and a spurious-free dynamic range of 108.5 dB at the sampling rate of 125 kS/s with the capacitor mismatch of 5%. The power consumption is 24.1 μW and the corresponding figure of merit (FoM) is 71.0 fJ/Conversion-step at 1.2 V.

A fully‐dynamic 6‐bit 3‐bit/cycle SAR ADC with a single differential DAC

This paper proposes a fully-dynamic 6-bit 3-bit/cycle SAR ADC. Unlike the prior multi-bit/cycle SAR ADCs that require several differential DACs or consume static power, the proposed SAR ADC needs only one differential DAC and is fully-dynamic. This helps reduce the circuit complexity, the ADC input capacitance, and the power consumption. Furthermore, its comparator outputs are directly fed back to the DAC array, without any complicated logics, which further reduces complexity. Finally, simulation results demonstrate the effectiveness of the proposed structure.

A 12.1bit-ENOB noise shaping SAR ADC for biosensor applications

This paper proposes a low power fully-passive noise shaping successive approximation register analog-to-digital converter (SAR ADC) for biosensor applications. The proposed ADC includes a second-order fully-passive integrator achieves a second-order noise transfer function. With an independent residue voltage generator to adjust common voltage between the main and residue path, the power efficiency of three differential inputs comparator is improved. The 0.18μm CMOS prototype chip occupies a total area of 1.37 mm2 with a core area of 0.58 mm2 and consumes 131 μW from a 1.3 V supply. The proposed SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 74.8 dB and a peak spurious-free dynamic range (SFDR) of 89.7 dB at a sampling rate of 8 MSPS and oversampling rate of 16, leading to the Schreier figure of merit (FoMs) of the proposed ADC of 167.4 dB.

A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system

In wireless implantable systems (WIS) low power consumption and linearity are the most prominent performance metrics in data acquisition systems. successive approximation register-analog to digital converter (SAR-ADC) is used for data processing in WIS. In this research work, a 10-bit low power high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC architecture is designed using the sample and hold (S/H) circuit consisting of a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latch comparator, a split capacitance digital to analog converter (SC-DAC) with mismatch calibration, and a SAR using D-flipflop. This architecture is designed in 45 nm CMOS technology. This ADC reduces non-linearity errors and improve the output voltage swing due to the usage of a clock booster and dummy switch in the sample and hold. The calculated outcomes of the proposed SAR ADC display that with on-chip calibration an ENOB of 9.38 (bits), spurious free distortion ratio (SFDR) of 58.621 dB, and ± 0.2 LSB DNL and ± 0.4LSB INL after calibration.

1.2 V 10‐bits 40 MS/s CMOS SAR ADC for low‐power applications

This article presents a 10-bits low-power successive approximation register analogue-to-digital converter (SAR ADC). The dual sampling technique was applied to the capacitive digital-to-analogue converter (CDAC), and the CDAC structure was constructed using a binary-weighted capacitor array and a C-2C capacitor array, simultaneously. Consequently, the CDAC structure enabled low-power consumption and a small layout area for the proposed SAR ADC. Moreover, the rail-to-rail operation of the bootstrapped circuit enabled the low-voltage ADC to be implemented, thereby improving the non-linearity. A prototype was designed and implemented using TSMC 0.18 μm CMOS 1P6M technology. This design achieved differential non-linearity and integral non-linearity of 0.36 least significant bit (LSB) and 0.45 LSB, respectively, and a signal-to-noise-and-distortion ratio of 56.7 dB and spurious-free dynamic range of 65.8 dB at the input frequency of 2 MHz. At a sampling rate of 40 MS/s with a single 1.2 V power supply, the power consumption was 736 μW. The proposed ADC achieved a figure-of-merit of 32.84 fJ/conversion-step. The ADC core occupied an active area of 195 × 241 μm 2 .

A 10-Bit 120 kS/s SAR ADC Without Reset Energy for Biomedical Electronics

A 10-bit 120 kS/s successive-approximation-register analog-to-digital converter (SAR ADC) is realized for implantable multichannel neural recording system. In order to reduce power consumption and area occupation, an improved energy-efficient VCM-based switching scheme is proposed. Different from the monotonic switching scheme, the switching procedure for each bit cycle of this proposed scheme is almost symmetrical, which facilitates the comparator design. Additionally, since all these capacitors are connected to VCM in the sampling phase, the reset energy of this switching scheme is zero. Bootstrapped sampling switches are employed for linearity improvement. Realized in 0.18-µm CMOS, the proposed ADC occupies an active area of 0.13 mm2. Including the I/O and two 4-to-1 multiplexers, the power consumption is 2.97 µW at 120 kS/s sampling rate. The figure-of-merit of this proposed SAR ADC is about 36.9 fJ/conversion-step.

A System-Level Correction SAR ADC with Noise-Tolerant Technique

A system-level correction successive approximation register analog-to-digital converter (SAR ADC) with regulated comparator of noise-tolerant technique is proposed. First, a substrate voltage boost technique is provided to improve the linearity and speed of sampling switch. Secondly, the proposed SAR ADC provides a comparator of noise regulation without redundant comparison cycle. The proposed comparator would be regulated in high-speed large noise state in large input differential signals. In the condition of small input differential signals, the comparator would be adjusted to low-speed small noise state. Furthermore, a high-speed low-power technique is proposed to optimize the performance of dynamic comparator. Additionally, a fast SAR logic structure is provided to increase the conversion speed of SAR ADC. To demonstrate the proposed techniques, a design example of SAR ADC is fabricated in 65[Formula: see text]nm CMOS technology. The SAR ADC is able to tolerate about 1.1 LSB noise errors in post-simulation with the operation state regulated automatically. The core occupies an active area of only 0.025[Formula: see text]mm2 and consumes 1.5[Formula: see text]mW. Measurement results achieve SFDR [Formula: see text][Formula: see text]dB and SNDR [Formula: see text][Formula: see text]dB, resulting in the FOM of 21.6[Formula: see text]fJ per conversion step.

A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices.

This paper presents a reference-voltage regulator free successive-approximation-register analog-to-digital converters (SAR ADC) with self-timed pre-charging for wireless-powered implantable medical devices. Assisted by a self-timed pre-charging technique, the proposed SAR ADC eliminates the need for a power-hungry reference-voltage regulator and area-consuming decoupling capacitor while maintaining insensitivity to the supply voltage fluctuation. Fabricated with a 0.18-µm complementary metal–oxide–semiconductor (CMOS) technology, the proposed SAR ADC achieves a Signal To Noise And Distortion Ratio (SNDR) of 53.32 dB operating at 0.8 V with a supply voltage fluctuation of 50 mVpp and consumes a total power of 2.72 µW at a sampling rate of 300 kS/s. Including the self-timed pre-charging circuits, the total figure-of-merit (FOM) is 23.9 fJ/conversion-step and the total area occupied is 0.105 mm2.

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to- Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non- binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv. Step which is comparable with existing ADC topologies.

A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS

This paper presents a 10bit 20 kS/s 9.1ENOB SAR ADC employing an energy-efficient and highly-linear capacitor switching strategy in 0.18 μm CMOS process. The SAR ADC with this proposed strategy features better linearity due to the use of a relatively lower assistant reference, the value of which is equivalent to a quarter of the input swing. In addition, the accuracy of the assistant reference has no impact on the ADC performance, since only this assistant reference will be involved with the capacitive DACs during the conversion period. The ADC is powered by the supplies of 0.6 V/0.15 V. The capacitive DACs are supplied by the 0.15 V assistant reference, while the other blocks are powered by the 0.6 V reference. In this case, the ADC consumes 11.7 nW overall, resulting in a figure-of-merit (FOM) of 1.6fJ/conversion-step. At a 20-kS/s output rate, the measured results show the proposed SAR ADC performs a peak signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB, a peak spurious-free-dynamic-range (SFDR) of 66.7 dB. The core area of the designed ADC is and 370 × 310 μm2.

An 8 bit 1 MS/s SAR ADC with 7.72-ENOB**Project supported by the National Natural Science Foundation of China (Nos. 61161003, 61264001, 61166004) and the Guangxi Key Laboratory of Precision Navigation Technology and Application Foundation (No. DH201501).

This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μW with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.

A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in 0.18-μm CMOS technology and occupies 0.728 mm2. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

저전력 복합 스위칭 기반의 0.16㎟ 12b 30MS/s 0.18um CMOS SAR ADC

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of . The proposed composite switching employs the conventional -based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the -based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

An asynchronous 12-bit 50 MS/s rail-to-rail Pipeline-SAR ADC in 0.18 μm CMOS

This paper presents a 12-bit 50MS/s asynchronous rail-to-rail Pipeline-SAR ADC. Design optimization is performed to achieve low power and high performance. The ADC consists of a 6-bit coarse SAR ADC, a residue amplifier and a 7-bit fine SAR ADC. A novel highly linear, power efficient switching scheme for the 2nd stage SAR ADC is proposed. The ADC operates asynchronously in order to simplify the design and save power. The ADC achieves low-power, high-resolution and high-speed operation without calibration. The ADC was fabricated in 0.18μm CMOS process with 1.8V power supply range. The proposed SAR ADC achieves 67.01dB SNDR and 77.13dB SFDR with sampling rate up to 50MS/s, corresponding to a figure-of-merit of 110fJ/conversion-step. The proposed ADC core occupies an active area of about 450×700µm2.

Combination of DAC switches and SAR logics in a 720 MS/s low-bit successive approximation ADC

In this paper a 4-bit 720 MHz low-power successive approximation register ADC is simulated in a 0.18 µm digital CMOS process. By using both of the 2-bit/step and time-interleaved techniques, a high sampling frequency is obtained. To simplify the SAR ADC in low-bit applications, the analog switches are eliminated and replaced with inherent digital switches of SAR logics. The power supply, resolution, sampling frequency, SNDR, and power consumption of the proposed SAR ADC are 1.8 V, 4-bit, 720 MHz, 22.1 dB, and 10 mW.