A fully‐dynamic 6‐bit 3‐bit/cycle SAR ADC with a single differential DAC

Abstract

This paper proposes a fully-dynamic 6-bit 3-bit/cycle SAR ADC. Unlike the prior multi-bit/cycle SAR ADCs that require several differential DACs or consume static power, the proposed SAR ADC needs only one differential DAC and is fully-dynamic. This helps reduce the circuit complexity, the ADC input capacitance, and the power consumption. Furthermore, its comparator outputs are directly fed back to the DAC array, without any complicated logics, which further reduces complexity. Finally, simulation results demonstrate the effectiveness of the proposed structure.