Programmable Logic Arrays Research Articles

Evaluation of Energy Efficient High Performance Power Gated Programmable Logic Array’s Under 65 nm Process Technology

The Programmable Logic Array (PLA) forms the major building block in the implementation of sequential and combinational functionalities in VLSI based embedded systems. Increased sub threshold leakage current resulting from the scaling down of the microprocessors carrying PLA causes high power dissipation. In order to improve the energy consumption of future electronic products, we propose a power gating method involving sleepy modes at transistor level implemented using 65 nm technology. This paper describes the design and analysis of PLA’s with footer switches for power gating. A comparative analysis has been made between the AND array, OR array and the inverter elements of the proposed PLA’s and the conventional one. Results produced through simulation confirms an optimized power reduction and the transient analysis of the proposed PLA models is proved to be much better than the conventional PLA.

Hardware implementation of a novel edge-map generation technique for pupil detection in NIR images

This paper proposes an edge-map generation technique for pupil detection in near infrared (NIR) images and its hardware implementation. The proposed edge-map generation technique is based on generating two different edge-maps of same eye image using Gaussian filtering, image binarization and Sobel edge detection operations and then combining them to a single edge-map using intersection operation on binary images. This technique reduces the false edges drastically in the edge-map of eye image, which is desirable for accurate and fast pupil detection. Field programmable logic array (FPGA) based hardware implementation of the proposed technique is presented, which can be used in iris localization system on FPGA based platforms for iris recognition application. The proposed edge-map generation hardware is a parallel-pipelined implementation.

A synchronous serial bus for multidimensional array acoustic logging tool

In high-temperature and spatial borehole applications, a distributed structure is employed in a multidimensional array acoustic logging tool (MDALT) based on a phased array technique for electronic systems. However, new challenges, such as synchronous multichannel data acquisition, multinode real-time control and bulk data transmission in a limited interval, have emerged. To address these challenges, we developed a synchronous serial bus (SSB) in this study. SSB works in a half-duplex mode via a master–slave architecture. It also consists of a single master, several slaves, a differential clock line and a differential data line. The clock line is simplex, whereas the data line is half-duplex and synchronous to the clock line. A reliable communication between the master and the slaves with real-time adjustment of synchronisation is achieved by rationally designing the frame format and protocol of communication and by introducing a scramble code and a Hamming error-correcting code. The control logic of the master and the slaves is realized in field programmable gate array (FPGA) or complex programmable logic device (CPLD). The clock speed of SSB is 10 MHz, the effective data rate of the bulk data transmission is over 99%, and the synchronous errors amongst the slaves are less than 10 ns. Room-temperature test, high-temperature test (175 °C) and field test demonstrate that the proposed SSB is qualified for MDALT.

Improved FPGA Implementation of Real Time Modified Mean Shift Tracking Algorithm

Objectives: To modify and implement color based mean shift object detection and tracking algorithm utilizing both the parallel and sequential capabilities of Xilinx ZYNQ ZC-702 SoC in order to speed up tracking. Method/ Statistical Analysis: The parallel and sequential processing capabilities of Field Programmable Logic Array (FPGA) and Processing System (PS) respectively are utilized in order to have a standalone system that can be faster, reliable and efficient while tracking the object in real time. Operations such as reading and writing video, grabbing kernel from frame and mean shift vector computation are sequential in nature and are best suited for processing system where as the operations parallel in nature are best fit for FPGA and may include estimation of histogram, computation of weights and estimation of weighted histogram. Executing them in parallel helps in reducing the machine cycles and enhances the fps. Findings: The high computational power of the algorithm is met by collective use of hardware and software while keeping the resources available on FPGA in check. The modified mean shift tracking method helps in exploiting the parallel computation capability of the FPGA. The paper compares the results with various techniques implemented on different embedded boards and the frame processing rate is much better with proposed FPGA implementation of modified mean shift tracking algorithm. Further, the window size can be varied without affecting fps. Application/Improvements: The frame rate achieved by using both hardware and software simultaneously is considerably higher than achieved with earlier implementations.

Versatile CCD‐based spectrometer with field programmable gate array controller core

The design and implementation of a novel room temperature charge-coupled device (CCD) spectrometer is presented. The timing generator and data acquisition circuits driving a 16,020 photodiode linear tricolour CCD detector capable of 24 dots per millimetre are described. Linear detection of ultraviolet, infrared and visible wavelengths over total wavelength range of 300 to 1000 nm of total wavelength range is possible by using three-colour array multiplexing. The field programmable gate array logic processing realises a low-cost, high-speed digital spectrometer with USB interface. A finite state automaton is used to generate low-skew, high-speed complex clocks to drive the system. The output of the instrument is 8 bit array intensity versus wavelength array acquired using semi-flash, 20 Mb/s analogue-to-digital converter, realising a 1.23 Gb/s per colour readout rate on the CCD. The resulting spectrometer is capable of USB 2.0 communication with high-level processing programmes.

Design and implementation of a real time demand side management under intermittent primary energy source conditions with a PV-battery backup system

This paper develops and implements a real time demand side management system on hardware in order to control unpredictable loads in a residential house application. The control is implemented under unreliable grid conditions with a high amount of energy blackouts, and complements a higher predictive control layer targeting predictable loads. A PV-battery backup system is installed in order to replace the grid during regular and frequent energy blackout periods that occur in various developing countries. The real time controller should enable or disable the operation of unpredictable devices in a reliable and fast manner according to preset priority levels applied by the user and available energy in the system. The aim of the controller is the prevention of the occurrence of a loss of power supply while respecting the operational constraints of the installed system. The developed control is implemented on the Zebdoard, which features a ZYNQ device combining dual-core ARM Cortex-A9 processors with traditional Field Programmable Gate Array (FPGA) logic fabric. The processor is programmed using an interrupt based strategy, the inputs and outputs of the control are linked to the FPGA of the ZYNQ. The simulation and implementation results show that the developed management program is highly flexible, accurate, fast, and reliable.

The design and implementation of a configurable MIMO detection system on the NOC-based multicore platform

This paper presents the design and implementation of a configurable and scalable MIMO detection system based on the multicore platform where the computation nodes are interconnected using the Network-on-Chip (NOC) paradigm. In this system, a tree-searching based MIMO detection algorithm is revised to be suitable for the NOC system, and the processing elements that execute the algorithm is architected. The mapping methodology of the algorithm onto the NOC platform is presented and the structure and operation of the entire MIMO detection scheme is illustrated. Furthermore, two types of NOC topologies are implemented in order to elucidate the design trade-offs between the processing speed and the system complexity. We show that the proposed MIMO detection scheme is highly configurable to support different system configurations including number of antennas and modulation schemes, and is suitable for large-scale MIMO system that equips with large number of antennas. The proposed NOC-based MIMO detection scheme has been implemented on the Field Programmable Logic Array (FPGA). The analyses of time complexity and experimental results based on the FPGA are both presented in this paper.

Design of QCA based Programmable Logic Array using decoder

A novel cost effective design of Programmable Logic Array (PLA) is proposed by recursive use of XOR gate, which is used to design 2×4, 3×8 and 4×16 decoders. The 4×16 decoder is coupled with an OR-Array to implement the proposed PLA using Quantum-dot Cellular Automata (QCA). The design is made effective by substantially reducing QCA wire crossing and cell count. A comparative study shows the minimization of cell count and clock-cycle delay of the XOR and Decoders. The PLA is utilized to design an efficient and delay effective 2 bit full adder.

DESIGN AND IMPLEMENTATION OF A MICROCONTROLLER BASED DUAL AXIS SOLAR RADIATION TRACKER

In this paper, an efficient microcontroller-based dual axis solar radiation tracker which can be used to align a single photovoltaic (PV) module or an array of module with the sun is implemented. It employs a dual axis tracking system in its control circuitry as against the popularly employed programmable logic array. Performance analysis of the dual axis solar tracker was conducted in a test bed in Department of Electrical and Electronics Engineering, Federal University of Petroleum Resources, Effurun, Nigeria and results showed that the power output of the photovoltaic (PV) system had 58.4 % improvement when compared with the traditional method of fixed solar panel. The dual axis system also has the benefit of reduction in the number of solar panels to be deployed because of the gains in power output and efficiency. http://dx.doi.org/10.4314/njt.v35i3.17

<b>Compatibility of Anfis controller and FPGA in solar power generation for a domestic oad

Among other soft computing techniques, the Adaptive Neuro Fuzzy Inference System (Anfis) gives a significant and advantageous result in solar power generation, especially in tracking the maximum power point. Due to the dynamic nature of solar irradiance and temperature, efficient energy conversion is not possible. However, advancements in the areas of artificial intelligence have made it possible to overcome the hurdles. The Maximum Power Point Tracking (MPPT) technique adopting the advantages of Anfis has been proven to be more successful with a fast dynamic response and high accuracy. The complete system is modeled using Matlab/Simulink; the hardware results are validated with the benefits of Field Programmable Logic Array (FPGA) instead of ordinary micro-controllers.

A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform

This article presents the Zynq UltraScale+ MPSoC (multiprocessor system on chip), which builds on the Zynq-7000 family. Compared to the first-generation Zynq, MPSoC increases performance and power efficiency while significantly improving the integration level between the SoC and the field-programmable gate array (FPGA). It also further raises the programming abstraction with the introduction of a new heterogeneous system-wide compiler. At the hardware level, system-wide coherency and shared virtual memory bridge across the processor subsystem into the programmable logic array. The new SDSoC (software-designed SoC) environment combines the ARM compiler with a high-level synthesis technology-based FPGA compiler and a full-system optimizing compiler to target all elements of the heterogeneous SoC from a common program source.

Experimental comparison of decomposition methods for systems of Boolean function

In this paper, we describe the results of the experimental comparison of programs that implement various decomposition methods for disjunctive normal forms of systems of completely defined Boolean functions. The complexity of a system of disjunctive normal forms is expressed in two ways: by the area of a programmable logic array that implements a system of disjunctive normal forms, or by the number of vertices of a binary decision diagram, which represents a system of Boolean functions. The complexity of the functional expansion of a system's functions is determined as the sum of the complexities of the subsystem of the functions included in this expansion. The estimates of the complexity are oriented on the synthesis of combinational circuits based on the programmed logical arrays and the library's logical elements.

Synthesis of reversible PLA using products sharing

Reversible logic is a computing design, where the ideal implementation would produce zero entropy gain. This unique feature causes prominent use of reversible computing. At the same time, more integration capability and regular structure for synthesizing large number of logic functions made programmable devices enthusiastic to use. In this paper, we propose design algorithm of one of the programmable logic devices, Programmable Logic Array (PLA) with a newly designed low cost 3 $$\times $$× 3 reversible Tara Babu (TB) gate, which can realize multi-output Exclusive-OR Sum of Product (ESOP) functions. In addition, we present a heuristic algorithm to sort and realize the product terms of ESOP functions in order to share the internal sub-products to reduce the number of gates in the proposed circuit. Proposed algorithms make the design more efficient with improvement 9.83 % in number of gates, 21.3 % in garbage outputs count and 14.75 % quantum cost parameters than the existing techniques averagely. Moreover, the area and power consumption of the proposed PLA are shown. Performance is also analyzed by using MCNC benchmark functions.

Demonstration of a directed XNOR/XOR optical logic circuit based on silicon Mach–Zehnder interferometer

We demonstrate a directed XNOR/XOR optical logic circuit based on silicon Mach–Zehnder interferometer. The device with the symmetric arm design is wavelength-insensitive in a wavelength range of 40nm. The device has an electro-optical bandwidth of around 20GHz. When the device is optically biased at the maximum or minimum transmission points by tuning the heater on one of its arms, it can perform the XNOR or XOR operations respectively at a speed up to 20Gbps. The high-speed and reconfigurable abilities of the device make it suitable for the future programmable optical logic array.

Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Abstract This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (−0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA

Recently, audio steganography has become an important covert communications technology. This technology hides secret data in a cover audio without perceptual modification of the cover audio. Most of the existing audio steganography techniques are unsuitable for real-time communication. Although field programmable logic array (FPGA) technologies offer parallel processing in hardware that can improve the speed of steganographic systems, the research activities in this area are very limited. This paper presents a parallel hardware-architecture for dual-mode audio steganography (DMAS) based FPGA technology. The proposed DMAS reconfigures the same hardware blocks in both hiding and recovery modes to reduce the hardware requirements. It has been successfully implemented on a Xilinx XC6SLX16 FPGA board to occupy only 97 slices. Furthermore, it processes data simultaneously at an operating frequency of up to 58.82MHz and accomplishes full message retrieval at an embedding rate of 25% with an audio quality above 45dB in terms of signal to noise ratio.

Logic Decomposition for PAL-Based CPLDs

The Programmable Array Logic (PAL)-based logic block is the core of the great majority of Complex Programmable Logic Devices (CPLDs). The purpose of this paper is to compare two models of decomposition dedicated to PAL-based devices. Non-standard usage of decomposition, which leads to the reduction of used PAL-based logic blocks in a programmable structure, is the aim of the presented methods. Each decomposition step is optimized for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The essence of decomposition models is oriented towards minimizing the number of PAL-based logic blocks used and adjusting the designed circuit to fit the structures of PAL-based blocks best. In the experimental section, a comparison of two decomposition models with the classical implementation approach is presented. Results of the experiments prove that the proposed methods lead to a significant reduction of chip area in relation to the classical approach, especially if CPLD structures consist of PAL-based blocks containing a relatively small number of product terms.

Memristor-CMOS logic and digital computational components

With the advent of memristor-CMOS (MCM) process that combines CMOS processing with nano-scale memristive devices, it becomes possible to reduce utilization of silicon area thus providing a promising option in the design of MCM based circuits. Two properties of memristor have attracted the most attention. Firstly its nanometer scale dimensions and, secondly, its nonvolatile memory characteristics. The nanometer scale feature of the device creates a new opportunity for new logic elements allowing realization of innovative circuits that are removed from the more established design domains. The non-volatile memory property enables us to realize new design methods for a variety of computational elements that lead to novel architectures. In this paper, we present primitive logic blocks based on MCM design style those are also extended to special logic types like Domino logic and programmable logic array (PLA). We also provide an overview of modeling principles that would allow designers to venture into this new integrated domain.

A compact and portable X-ray beam position monitor using Medipix3

The present work reports on the design and implementation of a novel portable X-ray beam diagnostics (XBPM) device. The device is transparent to the X-ray beam and provides real-time measurements of beam position, intensity, and size. The measurement principle is based on a pinhole camera which records scattered radiation from a Kapton foil which is placed in the beam path. The use of hybrid detectors (Medipix3) that feature a virtually noiseless readout system with capability of single photon detection and energy resolving power enables the diagnostics with a better resolution and higher sensitivity compared to the use of traditional indirect X-ray detection schemes. We describe the detailed system design, which consists of a vacuum compatible focal plane sensor array, a sensor conditioning and readout board and a heterogeneous data processing unit, which also acts as a network server that handles network communications with clients. The readout protocol for the Medipix3 sensor is implemented using field programmable gate array (FPGA) logic resulting in a versatile and scalable system that is capable of performing advanced functions such as data compression techniques and feature extraction. For the system performance measurements, we equipped the instrument with a single Medipix3 die, bump bonded to a Si sensor, rather than four for which it was designed. Without data compression, it is capable of acquiring magnified images and profiles of synchrotron X-ray beams at a transfer rate through Ethernet of 27 frames/s for one Medipix3 die.

Programmable logic circuits for functional integrated smart plastic systems

In this paper, we present a functional integrated plastic system. We have fabricated arrays of organic thin-film transistors (OTFTs) and printed electronic components driving an electrophoretic ink display up to 70mm by 70mm on a single flexible transparent plastic foil. Transistor arrays were quickly and reliably configured for different logic functions by an additional process step of inkjet printing conductive silver wires and poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) resistors between transistors or between logic blocks. Among the circuit functions and features demonstrated on the arrays are a 7-stage ring oscillator, a D-type flip-flop memory element, a 2:4 demultiplexer, a programmable array logic device (PAL), and printed wires and resistors. Touch input sensors were also printed, thus only external batteries were required for a complete electronic subsystem. The PAL featured 8 inputs, 8 outputs, 32 product terms, and had 1260 p-type polymer transistors in a 3-metal process using diode-load logic. To the best of our knowledge, this is the first time that a PAL concept with organic transistors has been demonstrated, and also the first time that organic transistors have been used as the control logic for a flexible display which have both been integrated on to a single plastic substrate. The versatility afforded by the additive inkjet printing process is well suited to organic programmable logic on plastic substrates, in effect, making flexible organic electronics more flexible.