Logic Decomposition for PAL-Based CPLDs

Abstract

The Programmable Array Logic (PAL)-based logic block is the core of the great majority of Complex Programmable Logic Devices (CPLDs). The purpose of this paper is to compare two models of decomposition dedicated to PAL-based devices. Non-standard usage of decomposition, which leads to the reduction of used PAL-based logic blocks in a programmable structure, is the aim of the presented methods. Each decomposition step is optimized for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The essence of decomposition models is oriented towards minimizing the number of PAL-based logic blocks used and adjusting the designed circuit to fit the structures of PAL-based blocks best. In the experimental section, a comparison of two decomposition models with the classical implementation approach is presented. Results of the experiments prove that the proposed methods lead to a significant reduction of chip area in relation to the classical approach, especially if CPLD structures consist of PAL-based blocks containing a relatively small number of product terms.