Synthesis of reversible PLA using products sharing

Abstract

Reversible logic is a computing design, where the ideal implementation would produce zero entropy gain. This unique feature causes prominent use of reversible computing. At the same time, more integration capability and regular structure for synthesizing large number of logic functions made programmable devices enthusiastic to use. In this paper, we propose design algorithm of one of the programmable logic devices, Programmable Logic Array (PLA) with a newly designed low cost 3 $$\times $$× 3 reversible Tara Babu (TB) gate, which can realize multi-output Exclusive-OR Sum of Product (ESOP) functions. In addition, we present a heuristic algorithm to sort and realize the product terms of ESOP functions in order to share the internal sub-products to reduce the number of gates in the proposed circuit. Proposed algorithms make the design more efficient with improvement 9.83 % in number of gates, 21.3 % in garbage outputs count and 14.75 % quantum cost parameters than the existing techniques averagely. Moreover, the area and power consumption of the proposed PLA are shown. Performance is also analyzed by using MCNC benchmark functions.