Processor Array Research Articles

A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition

As object recognition requires huge computation power to deal with complex image processing tasks, it is very challenging to meet real-time processing demands under low-power constraints for embedded systems. In this paper, a configurable heterogeneous multicore architecture with a dual-mode linear processor array and a cellular neural network on the network-on-chip platform is presented for real-time object recognition. The bio-inspired attention-based object recognition algorithm is devised to reduce computational complexity of the object recognition. The cellular neural network is utilized to accelerate the visual attention algorithm for selecting salient image regions rapidly. The dual-mode parallel processor is configured into single instruction, multiple data (SIMD) or multiple-instruction-multiple-data modes to perform data-intensive image processing operations while exploiting pixel-level and feature-level parallelisms required for the attention-based object recognition. The algorithm's hybrid parallelization strategy on the proposed architecture is adopted to obtain maximum performance improvement. The performance analysis results, using a cycle-accurate architecture simulator, show that the proposed architecture achieves a speedup of 2.8 times for the target algorithm over conventional massively parallel SIMD architecture at low hardware cost overhead. A prototype chip of the proposed architecture, fabricated in 0.13 mum complementary metal-oxide-semiconductor technology, achieves 22 frames/s real-time object recognition with less than 600 mW power consumption.

An 8$\times$8 Cell Analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13-$\mu{\hbox{m}}$ CMOS

This paper presents an integrated 8 times 8 cell image processor array demonstrating the parallel implementation of analog order-statistic filtering and grayscale mathematical morphology. Each cell, connected locally to four nearest neighbors and sized 30 times 28 mum2, includes a digitally programmable five-input analog current-mode ranked-order filter. The array also demonstrates an implementation of asynchronously propagating morphological grayscale reconstruction, which is robust against device mismatch. The measurement results of all programmable order-statistic operations are shown, verifying the correct operation of the array. The chip was manufactured in a 0.13- mum 1-poly 6-metal CMOS technology and operates from a single 1.3-V power supply.

A high speed programmable focal-plane SIMD vision chip

A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 × 64 pixel proof-of-concept chip was fabricated in a 0.35 μm standard CMOS process, with a pixel size of 35 μm × 35 μm. The chip can capture raw images up to 10,000 fps and runs low-level image processing at a framerate of 2,000–5,000 fps.

Common and Specific Contributions of the Intraparietal Sulci to Numerosity and Length Processing

Numerical and spatial magnitude processing have long been intimately associated, leading to the suggestion that they share a common system of magnitude representation. Although separate investigations on the cerebral areas involved in numerosity and spatial estimation point toward the parietal cortex, the precise anatomical overlap, if any, has not yet been directly established. Here, functional magnetic resonance imaging was used to localize the cerebral network involved in processing both numerosity and length. Blood oxygenation level-dependent signal changes were measured while healthy volunteers were making numerosity comparisons on linear arrays of dots, and length comparisons on discrete linear arrays of dots and continuous rectangles. The results show the bilateral involvement of parietal regions around the intraparietal sulci in explicit and implicit processing of numerosity, and a right lateralized occipitoparietal network activation in length processing; numerosity and length processing both activate the right IPS and the precentral gyrus. By excluding the mandatory intrinsic spatial processing of arrays, we demonstrate that the left IPS is involved in numerosity processing only, whereas the right IPS underlies a common processing mechanism or representation of spatial and numerical magnitude. Hum Brain Mapp 2009. (c) 2009 Wiley-Liss, Inc.

Increasing the specificity and function of DNA microarrays by processing arrays at different stringencies

DNA microarrays have for a decade been the only platform for genome-wide analysis and have provided a wealth of information about living organisms. DNA microarrays are processed today under one condition only, which puts large demands on assay development because all probes on the array need to function optimally under one condition only. Microarrays are often burdened with a significant degree of cross-hybridization, because of a poor combination of assay conditions and probe choice. As reviewed here, a number of promising microfluidics-based technologies can provide automatic processing of arrays under different assay conditions. These new array processors provide researchers and assay developers with novel possibilities to construct highly specific DNA arrays even towards regions of DNA greatly varying in G + C content. These array processors are also a powerful development tool for building arrays, because they combine high sample throughput with investigation of optimal assay conditions. The array processors can increase specificity in all DNA microarray assays, e.g. for gene expression, and microRNA and mutation analysis. Increased specificity of the array will also benefit microarray-based loci selection prior to high-throughput sequencing.

Minimizing interconnect length on reconfigurable meshes

Shorter total interconnect and fewer switches in a processor array definitely lead to less capacitance, power dissipation and dynamic communication cost between the processing elements. This paper presents an algorithm to find a maximum logical array (MLA) that has shorter interconnect and fewer switches in a reconfigurable VLSI array with hard/soft faults. The proposed algorithm initially generates the middle (⌊k/2⌋th) logical column and then makes it nearly straight for the MLA with k logical columns. A dynamic programming approach is presented to compact other logical columns toward the middle logical column, resulting in a tightly-coupled MLA. In addition, the lower bound of the interconnect length of the MLA is proposed. Experimental results show that the resultant logical array is nearly optimal for the host array with large fault size, according to the proposed lower bound.

Processing difficulties and instability of carbohydrate microneedle arrays

Background: A number of reports have suggested that many of the problems currently associated with the use of microneedle (MN) arrays for transdermal drug delivery could be addressed by using drug-loaded MN arrays prepared by moulding hot melts of carbohydrate materials. Methods: In this study, we explored the processing, handling, and storage of MN arrays prepared from galactose with a view to clinical application. Results: Galactose required a high processing temperature (160°C), and molten galactose was difficult to work with. Substantial losses of the model drugs 5-aminolevulinic acid (ALA) and bovine serum albumin were incurred during processing. While relatively small forces caused significant reductions in MN height when applied to an aluminium block, this was not observed during their relatively facile insertion into heat-stripped epidermis. Drug release experiments using ALA-loaded MN arrays revealed that less than 0.05% of the total drug loading was released across a model silicone membrane. Similarly, only low amounts of ALA (approximately 0.13%) and undetectable amounts of bovine serum albumin were delivered when galactose arrays were combined with aqueous vehicles. Microscopic inspection of the membrane following release studies revealed that no holes could be observed in the membrane, indicating that the partially dissolved galactose sealed the MN-induced holes, thus limiting drug delivery. Indeed, depth penetration studies into excised porcine skin revealed that there was no significant increase in ALA delivery using galactose MN arrays, compared to control (P value < 0.05). Galactose MNs were unstable at ambient relative humidities and became adhesive. Conclusion: The processing difficulties and instability encountered in this study are likely to preclude successful clinical application of carbohydrate MNs. The findings of this study are of particular importance to those in the pharmaceutical industry involved in the design and formulation of transdermal drug delivery systems based on dissolving MN arrays. It is hoped that we have illustrated conclusively the difficulties inherent in the processing and storage of carbohydrate-based dissolving MNs and that those in the industry will now follow alternative approaches.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

The Level-1 Trigger Muon Barrel System of the ATLAS experiment at CERN

The ATLAS Level-1 Muon Barrel Trigger is one of the main elements of the first stage of event selection of the ATLAS experiment at the Large Hadron Collider. The challenge of the Level-1 system is a reduction of the event rate from a collision rate of 40 MHz by a factor 103, using simple algorithms that can be executed in highly parallel custom electronics with a latency of the order of 1 μs. The input stage of the Level-1 Muon consists of an array of processors receiving the full granularity of data from a dedicated detector (Resistive Plate Chambers in the Barrel). This first stage of the algorithm is performed directly on-detector, while the final stage is performed in boards mounted in the counting room, by the so-called off-detector electronics. The trigger algorithm is executed within a fixed latency, its real-time output is the multiplicity of muon candidates passing a set of programmable pT thresholds, and their topological information. The detector system and the trigger electronics are designed to achieve a safe bunch-crossing identification. In order to optimize design effort and cost, the trigger system integrates also the readout of the detector, with its own requirements on time resolution and overall data bandwidth. We present the detailed functional requirements of the Level-1 Muon Barrel system, its architecture, implementation and construction.

Optimal Frequency Band Design Scheme of Dyadic Wavelet Processor Array Using Surface Acoustic Wave Devices

In this paper, the relationship between the center frequency and radius of bandwidth and its effect on the frequency band characteristics of dyadic wavelet processor array using surface acoustic wave (SAW) devices are studied, and an optimal frequency band design scheme is proposed. For an arbitrary scale wavelet processor, we proposed that the center frequency is defined to three times of the radius of frequency bandwidth. The frequency band design scheme ensures that the frequency band coverage factor is equal to 100% at -3 dB, which avoid the signal loss caused by the discrete frequency band and the device waste caused by the redundant frequency band. With the frequency band design scheme, an experiment of implementing a dyadic wavelet processor array using SAW devices with five scales is presented. Experimental results confirm that the frequency band coverage factor equals 100% at -3 dB without discrete and redundant frequency band.

Common and specific contributions of the intraparietal sulci to numerosity and length processing

Numerical and spatial magnitude processing have long been intimately associated, leading to the suggestion that they share a common system of magnitude representation. Although separate investigations on the cerebral areas involved in numerosity and spatial estimation point toward the parietal cortex, the precise anatomical overlap, if any, has not yet been directly established. Here, functional magnetic resonance imaging was used to localize the cerebral network involved in processing both numerosity and length. Blood oxygenation level-dependent signal changes were measured while healthy volunteers were making numerosity comparisons on linear arrays of dots, and length comparisons on discrete linear arrays of dots and continuous rectangles. The results show the bilateral involvement of parietal regions around the intraparietal sulci in explicit and implicit processing of numerosity, and a right lateralized occipitoparietal network activation in length processing; numerosity and length processing both activate the right IPS and the precentral gyrus. By excluding the mandatory intrinsic spatial processing of arrays, we demonstrate that the left IPS is involved in numerosity processing only, whereas the right IPS underlies a common processing mechanism or representation of spatial and numerical magnitude.

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations, reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A 32 × 32 cell parallel analog test array for reference-shift with a maximum block-size of 16 × 16, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 µm CMOS technology.

A Case Study for NoC-Based Homogeneous MPSoC Architectures

The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processor.

Arquitetura multiprocessada e reconfigurável para a síntese de redes de Petri em hardware

Uma arquitetura reconfigurável e multiprocessada para a implementação física de Redes de Petri foi desenvolvida em VHDL e mapeada sobre um FPGA. Convencionalmente, as Redes de Petri são transformadas em uma linguagem de descrição de hardware no nível de transferências entre registradores e um processo de síntese de alto nível é utilizado para gerar as funções booleanas e tabelas de transição de estado para que se possa, finalmente, mapeá-las num FPGA (Morris et al., 2000) (Soto and Pereira, 2001). A arquitetura proposta possui blocos lógicos reconfiguráveis desenvolvidos exclusivamente para a implementação dos lugares e das transições da rede, não sendo necessária a descrição da rede em níveis de abstração intermediários e nem a utilização de um processo de síntese para realizar o mapeamento da rede na arquitetura. A arquitetura permite o mapeamento de modelos de Redes de Petri com diferenciação entre as marcas e associação de tempo no disparo das transições, sendo composta por um arranjo de processadores reconfiguráveis, cada um dos quais representando o comportamento de uma transição da Rede de Petri a ser mapeada e por um sistema de comunicação, implementado por um conjunto de roteadores que são capazes de enviar pacotes de dados de um processador reconfigurável a outro. A arquitetura proposta foi validada num FPGA de 10.570 elementos lógicos com uma topologia que permitiu a implementação de Redes de Petri de até 9 transições e 36 lugares, atingindo uma latência de 15,4ns e uma vazão de até 17,12GB/s com uma freqüência de operação de 64,58MHz.

Local rather than global processing of visual arrays in numerosity discrimination by pigeons (Columba livia)

A series of experiments investigated which stimulus properties pigeons use when they discriminate pairs of visual arrays that differ in numerosity. Transfer tests with novel stimuli confirmed that the birds' choices were based on relative differences in numerosity. However, pigeons differed from other species in the non-numerical cues that affected their choices. In human and non-human primates, numerical discrimination is often influenced by continuous variables such as surface area or overall stimulus brightness. Pigeons showed little evidence of using those cues, even when summed area and brightness had been correlated with numerosity differences and reward outcome. But when array-element sizes were asymmetrically distributed across numerosities, the birds readily utilized information about item sizes as an additional discriminative cue. These novel results are discussed in relation to pigeons' tendency to focus on local, rather than global dimensions when they process other non-numerical complex visual stimuli. The findings suggest there may be inter-specific differences in the type of perceptual information that provides the input stage for mechanisms underlying numerical processing.

A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network‐On‐Chips

We present a heuristic algorithm for the run‐time distribution of task sets in a homogeneous Multiprocessor network‐on‐chip. The algorithm is itself distributed over the processors and thus can be applied to systems of arbitrary size. Also, tasks added at run‐time can be handled without any difficulty, allowing for inline optimisation. Based on local information on processor workload, task size, communication requirements, and link contention, iterative decisions on task migrations to other processors are made. The mapping results for several example task sets are first compared with those of an exact (enumeration) algorithm with global information for a 3 × 3 processor array. The results show that the mapping quality achieved by our distributed algorithm is within 25% of that of the exact algorithm. For larger array sizes, simulated annealing is used as a reference and the behaviour of our algorithm is investigated. The mapping quality of the algorithm can be shown to be within a reasonable range (below 30% mostly) of the reference. This adaptability and the low computation and communication overhead of the distributed heuristic clearly indicate that decentralised algorithms are a favourable solution for an automatic task distribution.

High-performance, low-power architecture for scalable radix 2 montgomery modular multiplication algorithm

This paper presents a new processor array architecture for scalable radix 2 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architecture extracted by C. Koc. Also, the multiplier bits are fed serially to the first processing element of the processor array every odd clock cycle. By analyzing this architecture, we found that it has a better performance-in terms of area and speed-and lower power consumption than the previous architecture extracted by C. Koc.

IVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor

iVisual, an intelligent visual sensor SoC integrating 2790 fps CMOS image sensor and 76.8 GOPS, 374 mW vision processor, is implemented on a 7.5 mm t 9.4 mm die in a UMC 0.18 mum CMOS Image Sensor process. Light-in, answer-out SoC architecture is adopted to avoid possible privacy problems. A feature processor is designed to eliminate the dataflow mismatch between processor array and scalar processor to increase 36% of average throughput. To increase hardware utilization, an inter-processor synchronization scheme is adopted to increase 23% of average throughput. Memory access is reduced by 94% to save 726 mW of power consumption. A bitplane-based single port memory structure is adopted to reduce SRAM area. The 205 GOPS/W power efficiency and 1.16 GOPS/mm2 area efficiency are therefore achieved by use of the proposed techniques.

A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays

For developing design environment of various Dynamically Reconfigurable Processor Arrays (DRPAs), the Graph with Configuration Information (GCI) is proposed to represent configurable resource in the target dynamically reconfigurable architecture. The functional unit, constant unit, register, and routing resource can be represented in the graph as well as the configuration information. The restriction in the hardware is also added in the graph by limiting the possible configuration at a node controlled by the other node. A prototype compiler called Black-Diamond with GCI is now available for three different DRPAs. It translates data-flow graph from C-like front-end description, applies placement and routing by using the GCI, and generates configuration data for each element of the DRPA. Evaluation results of simple applications show that Black-Diamond can generate reasonable designs for all three different architectures. Other target architectures can be easily treated by representing many aspects of architectural property into a GCI.

Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing

This paper presents an FPGA realisation of an application-specific cellular processor array designed for asynchronous skeletonization of binary images. The skeletonization algorithm is based on ite...