Processor Array Research Articles

Fabrication of electrodes with ultralow platinum loading by RF plasma processing of self-assembled arrays of Au@Pt nanoparticles

Conductive, carbon-free, electrocatalytically active, nanostructured electrodes with ultra-low platinum loading were fabricated using self-assembly of octadecanethiol-coated Au@Pt nanoparticles followed by RF plasma treatment. Bilayer arrays of Au@Pt nanoparticles with platinum loadings of 0.50, 1.04, 1.44, and 1.75 μg cm−2 (corresponding to 0.5, 1, 1.5 and 2 atomic layer coverage of platinum on nominally 5 nm gold core) were subjected to RF argon plasma treatment for various durations and their electrical conductivity, morphological evolution, and electrocatalytic activity characterized. Samples with monolayer and above platinum coverages exhibit maximum electrochemically active surface areas values of ∼100 m2/gpt and specific activities that are ∼4× to 6× of a reference platinum nanoparticle bilayer array. The underlying gold core influences the structural evolution of the samples upon RF plasma treatment and leads to the formation of highly active Pt(110) facets on the surface at an optimal plasma treatment duration, which also corresponds to the onset of a sharp decline in lateral sheet resistance. The sample having a two atom thick platinum coating has the highest total mass activity of 48 ± 3 m2/g(pt+au), corresponding to 44% Pt atom utilization, while also exhibiting enhanced CO tolerance as well as high methanol oxidation reaction and oxygen reduction reaction activity.

Reconfigurable Hardware Accelerator for Profile Hidden Markov Models

We propose a processor array accelerator for profile hidden Markov models of the Viterbi algorithm. The proposed processor array has the advantage that it can be modified to enable hardware reuse rather than replicating processing elements of the processor array on a cluster of FPGAs. Also, it has the advantage of reducing the area overhead of the FPGA compared to the previously published conventional processor arrays. This allows for increasing the number of processing elements and the system throughput. The proposed processor array and the previously reported conventional one are coded using the VHDL language and implemented using the FPGA technology. The implementation results showed that the proposed design achieves 1.31× to 1.75×speedup and saves area ranging from 24.4 to 34.0% over the conventional design for profile HMM query lengths ranging from 38 to 2295.

Real-Time Signal Processing of Massive Sensor Arrays via a Parallel Fast Converging SVD Algorithm: Latency, Throughput, and Resource Analysis

This paper introduces a parallel fast converging Jacobi-like singular value decomposition (SVD) algorithm applicable to real-time signal processing of massive sensor arrays. The proposed algorithm highly increases the SVD convergence rate for larger matrices when compared with traditional Jacobi-based methods. A highly modular system design is proposed, which retains the parallel nature of the Jacobi methods key to real-time implementation intended for field programmable gated arrays (FPGAs). The proof of design was provided via an implementation on Virtex-6 FPGA, and the improvement in performance was verified via simulations. The proposed design was compared with the traditional design in terms of FPGA resource consumption, maximum achievable frequency, and latency throughput tradeoff.

Modern methods of experimental construction of texture complete direct pole figures by using X-ray data

Currently used methods for constructing texture complete direct pole figure (CDPF) based on the results of X-ray diffractometric measurements were considered with respect to the products of Zr-based alloys and, in particular, used in a nuclear reactor cladding tubes, for which the accuracy of determination of integral texture parameters is of the especial importance. The main attention was devoted to technical issues which are solved by means of computer processing of large arrays of obtained experimental data. Among considered questions there are amendments of the defocusing, techniques for constructing of complete direct pole figures and determination of integral textural parameters. The methods of reconstruction of complete direct pole figures by partial direct pole figures recorded up to tilt angles of sample ψ=70-80°: the method of extrapolation of data to an uninvestigated region of the stereographic projection, and the method of "sewing" of partial pole figures measured for three mutually perpendicular plane sections of the product. The limits of applicability of these methods, depending on the shape of the test product and the degree of inhomogeneity of the layer-by-layer texture, were revealed. On the basis of a large number of experimental data, the accuracy of the integral parameters used for calculation of the physical and mechanical properties of metals with a hexagonal crystal structure was found to be equal to 0.02, when taking into account the texture heterogeneity of regular products from Zr-based alloys.

High speed vision processor with reconfigurable processing element array based on full-custom distributed memory

In this paper, a hybrid vision processor based on a compact full-custom distributed memory for near-sensor high-speed image processing is proposed. The proposed processor consists of a reconfigurable processing element (PE) array, a row processor (RP) array, and a dual-core microprocessor. The PE array includes two-dimensional processing elements with a compact full-custom distributed memory. It supports real-time reconfiguration between the PE array and the self-organized map (SOM) neural network. The vision processor is fabricated using a 0.18 µm CMOS technology. The circuit area of the distributed memory is reduced markedly into 1/3 of that of the conventional memory so that the circuit area of the vision processor is reduced by 44.2%. Experimental results demonstrate that the proposed design achieves correct functions.

Justification of computational methods to ensure information management systems

Summary. Due to the diversity and complexity of organizational management tasks a large enterprise, the construction of an information management system requires the establishment of interconnected complexes of means, implementing the most efficient way collect, transfer, accumulation and processing of information necessary drivers handle different ranks in the governance process. The main trends of the construction of integrated logistics management information systems can be considered: the creation of integrated data processing systems by centralizing storage and processing of data arrays; organization of computer systems to realize the time-sharing; aggregate-block principle of the integrated logistics; Use a wide range of peripheral devices with the unification of information and hardware communication. Main attention is paid to the application of the system of research of complex technical support, in particular, the definition of quality criteria for the operation of technical complex, the development of information base analysis methods of management information systems and define the requirements for technical means, as well as methods of structural synthesis of the major subsystems of integrated logistics. Thus, the aim is to study on the basis of systematic approach of integrated logistics management information system and the development of a number of methods of analysis and synthesis of complex logistics that are suitable for use in the practice of engineering systems design. The objective function of the complex logistics management information systems is the task of gathering systems, transmission and processing of specified amounts of information in the regulated time intervals with the required degree of accuracy while minimizing the reduced costs for the establishment and operation of technical complex. Achieving the objective function of the complex logistics to carry out certain organization of interaction of information converters, which are the building blocks of integrated logistics, and their interaction is provided by the construction of the structure of the complex logistics.

Micromagnet arrays enable precise manipulation of individual biological analyte-superparamagnetic bead complexes for separation and sensing.

In this article, we review lab on a chip (LOC) devices that have been developed for processing magnetically labelled biological analytes, e.g., proteins, nucleic acids, viruses and cells, based on micromagnetic structures and a time-varying magnetic field. We describe the methods that have been developed for fabricating micromagnetic arrays and the bioprocessing operations that have been demonstrated using superparamagnetic (SPM) beads, i.e., programmed transport, switching, separation of specific analytes, and pumping and mixing of fluids in microchannels. The primary advantage of micromagnet devices is that they make it possible to develop systems that control individual SPM beads, enabling high-efficiency separation and analysis. These devices do not require hydrodynamic control and lend themselves to parallel processing of large arrays of SPM beads with modest levels of power consumption. Micromagnet devices are well suited for bioanalytical applications that require high-resolution separation, e.g., detection of rare cell types such as circulating tumour cells, or biosensor applications that require multiple magnetic bioprocessing operations on a single chip.

Justification of computational methods to ensure information management systems

Summary. Due to the diversity and complexity of organizational management tasks a large enterprise, the construction of an information management system requires the establishment of interconnected complexes of means, implementing the most efficient way collect, transfer, accumulation and processing of information necessary drivers handle different ranks in the governance process. The main trends of the construction of integrated logistics management information systems can be considered: the creation of integrated data processing systems by centralizing storage and processing of data arrays; organization of computer systems to realize the time-sharing; aggregate-block principle of the integrated logistics; Use a wide range of peripheral devices with the unification of information and hardware communication. Main attention is paid to the application of the system of research of complex technical support, in particular, the definition of quality criteria for the operation of technical complex, the development of information base analysis methods of management information systems and define the requirements for technical means, as well as methods of structural synthesis of the major subsystems of integrated logistics. Thus, the aim is to study on the basis of systematic approach of integrated logistics management information system and the development of a number of methods of analysis and synthesis of complex logistics that are suitable for use in the practice of engineering systems design. The objective function of the complex logistics management information systems is the task of gathering systems, transmission and processing of specified amounts of information in the regulated time intervals with the required degree of accuracy while minimizing the reduced costs for the establishment and operation of technical complex. Achieving the objective function of the complex logistics to carry out certain organization of interaction of information converters, which are the building blocks of integrated logistics, and their interaction is provided by the construction of the structure of the complex logistics.

Data Acquisition for the New Muon g-2 Experiment at Fermilab

A new measurement of the anomalous magnetic moment of the muon,aμ≡ (g – 2)/2, will be performed at the Fermi National Accelerator Laboratory. The most recent measurement, performed at Brookhaven National Laboratory and completed in 2001, shows a 3.3-3.6 standard deviation discrepancy with the Standard Model predictions for aμ. The new measurement will accumulate 21 times those statistics, measuring aμ to 140 ppb and reducing the uncertainty by a factor of 4.The data acquisition system for this experiment must have the ability to record deadtime-free records from 700 μs muon spills at a raw data rate of 18 GB per second. Data will be collected using 1296 channels of μTCA-based 800 MHz, 12 bit waveform digitizers and processed in a layered array of networked commodity processors with 24 GPUs working in parallel to perform a fast recording and processing of detector signals during the spill. The system will be controlled using the MIDAS data acquisition software package. The described data acquisition system is currently being constructed, and will be fully operational before the start of the experiment in 2017.

Algorithm for dealing with time‐varying signal within sliding‐window for harmonics estimation

In many state-of-the-art signal processing techniques, a signal within sliding-window (SW) is assumed stationary for analysing non-stationary signals. Whenever this assumption is violated, inaccuracies increase to the unacceptable levels. A narrow window-width is recommended for limiting the effect of variations within window, however, it results in poor frequency resolution and demands for increased computational resources. This study presents a simple and efficient algorithm to address amplitude-variation in a signal within SW, thus, allowing time resolution of 1-cycle and frequency resolution of 5 Hz (as per IEC Std. 61000-4-7) with improved accuracy and reliability of the fast Fourier transform of the time-varying signal. The proposed algorithm computes and applies necessary corrections to provide accurate estimates of the integer harmonics for the most recent cycle, irrespective of the number of cycles within the SW. The proposed algorithm is computationally efficient and fast, therefore, can be implemented easily either on digital signal processor or field programmable gate arrays hardware platform. The salient features of the proposed algorithm have been validated on variety of simulated and experimental signals, and have been compared with similar existing techniques in practice nowadays.

Resource-awareness on heterogeneous MPSoCs for image processing

Explore the benefits of using heterogeneous MPSoC for image processing.Different types of processing elements leads to programming issues on MPSoC.The conventional scheme (static mapping) does not achieve the best results.A case-study based on resource-aware programming model named Invasive Computing.The resource-aware model leads to better quality and lower latency on MPSoC. Multiprocessor system-on-chip (MPSoC) designs offer a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding massively parallel processor arrays (MPPA) and specialized hardware with instruction-set extensions. On-chip MPPAs can be used to accelerate low-level image-processing algorithms with massive inherent parallelism. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping, among others. The conventional approach used for programming heterogeneous MPSoCs results in a static mapping of various parts of the application to different PE types, based on the nature of the algorithm and the structure of the PEs. Yet, such a mapping scheme independent of the instantaneous load on the PEs may lead to under-utilization of some type of PEs while overloading others.In this work, we investigate the benefits of using a heterogeneous MPSoC for accelerating various stages within a real-world image-processing algorithm for object-recognition. A case study demonstrates that a resource-aware programming model called Invasive Computing helps to improve the throughput and worst observed latency of the application program, by dynamically mapping applications to different types of PEs available on a heterogeneous MPSoC.

Techniques for on-demand structural redundancy for massively parallel processor arrays

Abstract In this paper, we present techniques for providing on-demand structural redundancy for Coarse-Grained Reconfigurable Array (CGRAs) and a calculus for determining the gains of reliability when applying these replication techniques from the perspective of safety-critical parallel loop program applications. Here, for protecting massively parallel loop computations against errors like soft errors, well-known replication schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) must be applied to each single Processor Element (PE) rather than one based on application requirements for reliability and Soft Error Rates (SERs). Moreover, different voting options and signal replication schemes are investigated. It will be shown that hardware voting may be accomplished at negligible hardware cost, i. e. less than two percent area overhead per PE, for a class of reconfigurable processor arrays called Tightly Coupled Processor Arrays (TCPAs). As a major contribution of this paper, a formal analysis of the reliability achievable by each combination of replication and voting scheme for parallel loop executions on CGRAs in dependence of a given SER and application timing characteristics (schedule) is elaborated. Using this analysis, error detection latencies may be computed and proper decisions which replication scheme to choose at runtime to guarantee a maximal probability of failure on-demand can be derived. Finally, fault-simulation results are provided and compared with the formal analysis of reliability.

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

With the increased density of three-dimensional (3D) processor arrays, faults can potentially occur quite often due to power overheating during massively parallel computing. In order to achieve fault-tolerance under such a scenario, an effective way is to find an as large as possible logical fault-free subarray of $m^{\prime }\;\times\;$ $n^{\prime }\;\times\;$ $h^{\prime }$ from a faulty array of $m\;\times\;$ $n\;\times\;$ $h$ ( $m^{\prime }$ $\;\le\;$ $m,n^{\prime }$ $\;\le\;$ $n, h^{\prime }$ $\;\le\;$ $h$ ), such that an original application can still work on the $m^{\prime }\;\times\;$ $n^{\prime }\;\times\;$ $h^{\prime }$ subarray. This paper investigates the problem of constructing maximum fault-free subarrays with minimum interconnection length from 3D arrays with faults. First, we prove that constructing maximum logical array (MLA) is NP-complete. We propose a linear-time algorithm which is capable of producing an MLA for the problem with the constraint of selected indexes. Second, we prove that minimizing the interconnection length (inter-length) of the MLA is NP-hard. We propose an efficient heuristic which significantly reduces the inter-length by revising each logical plane of the MLA. This leads to the reduction of communication cost, capacitance and dynamic power dissipation. In addition, we propose a lower bound for the inter-length of the MLA to evaluate the proposed algorithms. Simulation results show that, the size of logical array can be improved up to 62.6 percent in average, and the inter-length redundancy can be reduced by 22.7 percent in average, compared to the state-of-the-art, for all cases considered.

Flow Boiling in an In-Line Set of Short Narrow Gap Channels

Heat transfer coefficients in a set of three symmetrically heated narrow gap channels arranged in line are reported at power densities of 1 kW/cm3 and wall heat flux of 3–40 W/cm2. This configuration emulates an electronics system wherein power dissipation can vary across an array of processors, memory chips, or other components. Three pairs of parallel ceramic resistance heaters in a nearly adiabatic housing form the flow passage, and length-to-gap ratios for each pair of heaters are 34 at a gap of 0.36 mm. Novec™ 7200 and 7300 are used as the heat transfer fluids. Nonuniform longitudinal power distributions are designed with the center heater pair at 1.5X and 2X the level of the first and third heater pairs. At all levels of inlet subcooling, single-phase heat transfer dominates over the first two heater pairs, while the third pair exhibits significant increases because of the presence of flow boiling. Reynolds numbers range from 250 to 1200, Weber numbers from 2 to 14, and boiling numbers from O(10−4) to O(10−3). Exit quality can reach 30% in some cases. Overall heat transfer coefficients of 40 kW/m2K are obtained. Pressure drops for both Novec™ heat transfer fluids are approximately equal at a given mass flux, and a high ratio of heat transfer to pumping power (coefficient of performance (COP)) is obtained. With a mass flux of 250 kg/m2s, heater temperatures can exceed 95 °C, which is the acceptable limit of steady operation for contemporary high performance electronics. Thus, an optimal operating point involving power density, power distribution, mass flux, and inlet subcooling is suggested by the data set for this benchmark multiheater configuration.

Visual search is postponed during the period of the AB: An event-related potential study.

In the phenomenon known as the attentional blink (AB), perception of the second of two rapidly sequential targets (T2) is impaired when presented shortly after the first (T1). Studies in which T2 consisted of a pop-out search array provided evidence suggesting that visual search is postponed during the AB. In the present work, we used behavioral and electrophysiological measures to test this postponement hypothesis. The behavioral measure was reaction time (RT) to T2; the electrophysiological measure was the onset latency of an ERP index of attentional selection, known as the N2pc. Consistent with the postponement hypothesis, both measures were delayed during the AB. The delay in N2pc was substantially shorter than that in RT, pointing to multiple sources of delay in the chain of processing events, as distinct from the single source postulated in current theories of the AB. Finally, the finding that the N2pc was delayed during the AB strongly suggests that attention is involved in the processing of pop-out search arrays.

Tunable hyperbolic apodizer

We unveil the use of two grey level masks for controlling continuously the attenuation of a spatial filter, which has an exponentially decreasing hyperbolic profile. We present analytical expressions that help to visualize the influence of our proposed grey level masks for reducing the side-lobes of a 1-D point spread function. Full Text: PDF References P. Jacquinot and B. Roizen-Dossier, "Apodisation," in Prog. Opt. 3, E. Wolf editor (North Holland, 1964) pp. 29-186. DirectLink C. W. McCutchen, "Generalized Aperture and the Three-Dimensional Diffraction Image", J. Opt. Soc. Am. 54, 240 (1964). CrossRef H. Arsenault and A. Boivin, "An Axial Form of the Sampling Theorem and its Application to Optical Diffraction", J. Appl. Phys. 38, 3988 (1967). CrossRef C. W. McCutchen, "Convolution relation within the three-dimensional diffraction image", J. Opt. Soc. Am. A 8, (1991). CrossRef J. E. A. Landgrave and L. R. Berriel-Valdos, "Sampling expansions for three-dimensional light amplitude distribution in the vicinity of an axial image point", J. Opt. Soc. Am. A 14, 2962 (1997). CrossRef A.W. Lohmann, J. Ojeda-Casta-eda and P. Rodríguez-Montero, "Axial irradiance shaping with binary polar curves", Opt. Comm. 108, 42 (1994). CrossRef J. Ojeda-Castafieda, L. R. Berriel-Valdos, and E. Montes, "Bessel annular apodizers: imaging characteristics", Appl. Opt. 26, 2770 (1987). CrossRef J. Ojeda-Casta-eda, and A. Díaz, "High focal depth by quasibifocus", Appl. Opt. 27, 4163 (1988). CrossRef J. Ojeda-Casta-eda and L. R. Berriel-Valdos, "Arbitrarily high focal depth with finite apertures", Opt. Lett. 13, 183 (1988). CrossRef J. Ojeda-Casta-eda and L. R. Berriel-Valdos, "Zone plate for arbitrarily high focal depth", Appl. Opt. 29, 994 (1990). CrossRef J. Ojeda-Casta-eda, E. Yépez-Vidal and E. García-Almanza, "Optical processor arrays for controlling focal length or for tuning the depth of field", Phot. Lett. of Poland 2, 162 (2010). DirectLink Jorge Ojeda-Castaneda, Emmanuel Yépez-Vidal, Eloy García-Almanza, and Cristina M. Gómez-Sarabia, "Tunable axial bursts using annularly distributed phase masks", Phot. Lett. of Poland 4, 115 (2012). DirectLink Jorge Ojeda-Castaneda, Sergio Ledesma and Cristina M. Gómez-Sarabia, "Hyper Gaussian windows with fractional wavefronts", Phot. Lett. of Poland 5, 23 (2013). CrossRef W. W. Bell, Special functions for scientists and engineers (Van Nostrand, London, 1968)

A Survey of Paradigms for Building and Designing Parallel Computing Machines

In this paper we describe paradigms for building and designing parallel computing machines. Firstly we elaborate the uniqueness of MIMD model for the execution of diverse applications. Then we compare the General Purpose Architecture of Parallel Computers with Special Purpose Architecture of Parallel Computers in terms of cost, throughput and efficiency. Then we describe how Parallel Computer Architecture employs parallelism and concurrency through pipelining. Since Pipelining improves the performance of a machine by dividing an instruction into a number of stages, therefore we describe how the performance of a vector processor is enhanced by employing multi pipelining among its processing elements. Also we have elaborated the RISC architecture and Pipelining in RISC machines After comparing RISC computers with CISC computers we observe that although the high speed of RISC computers is very desirable but the significance of speed of a computer is dependent on implementation strategies. Only CPU clock speed is not the only parameter to move the system software from CISC to RISC computers but the other parameters should also be considered like instruction size or format, addressing modes, complexity of instructions and machine cycles required by instructions. Considering all parameters will give performance gain . We discuss Multiprocessor and Data Flow Machines in a concise manner. Then we discuss three SIMD (Single Instruction stream Multiple Data stream) machines which are DEC/MasPar MP-1, Systolic Processors and Wavefront array Processors. The DEC/MasPar MP-1 is a massively parallel SIMD array processor. A wide variety of number representations and arithmetic systems for computers can be implemented easily on the DEC/MasPar MP-1 system. The principal advantages of using such 64×64 SIMD array of 4-bit processors for the implementation of a computer arithmetic laboratory arise out of its flexibility. After comparison of Systolic Processors with Wave front Processors we found that both of the Systolic Processors and Wave front Processors are fast and implemented in VLSI. The major drawback of Systolic Processors is the problem of availability of inputs when clock ticks because of propagation delays in connection buses. The Wave front Processors combine the Systolic Processor architecture with Data Flow machine architecture. Although the Wave front processors use asynchronous data flow computing structure, the timing in the interconnection buses, at input and at output is not problematic..

Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs

Matrix algorithms are an important part of many digital signal processing applications as they are core kernels that are usually required to be applied many times while computing different tasks. Hardware assisted implementations using FPGAs provide a good compromise between performance, cost and power consumption, specially when high level synthesis techniques are employed for deriving co-processors. In this paper a high level synthesis approach to generate embedded processor arrays for matrix algorithms based on the polytope model is presented. The proposed approach provides a solution for efficient data memory accesses and data transferring for feeding the processor array, as well as support for solving problems independently of their size and limited only by the FPGA available resources. The proposed approach has been validated by generating processor arrays for three different matrix algorithms used in digital signal processing applications; more precisely matrix–matrix multiplication, Cholesky and LU decomposition algorithms. These algorithms were targeted for a Spartan-6 device and compared against their sequential implementations targeted for a MicroBlaze processor in order to provide a general view of the gain achieved by the processor arrays when the arrays and sequential processors are implemented in the same technology. Results show that the implemented arrays outperforms hardware and software implementations considering an embedded platforms scenario with a Spartan-6 device.

Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing

This paper presents the design and the VLSI implementation of an asynchronous cellular logic array for fast binary image processing. The proposed processor array employs trigger-wave propagation and collision detection mechanisms for binary image skeletonization, and Voronoi tessellation. Low power, low area, and high processing speed are achieved using full custom dynamic logic design. The prototype array consisting of 64 $\times$ 96 cells is fabricated in a standard 90 nm CMOS technology. The experimental results confirm the fast operation of the array, capable of extracting up to $2.78\times 10^{6}$ skeletons per second, consuming less than 1 nJ/skeleton. The asynchronous operation enables circular wave contours, which improves the quality of the extracted skeletons. The proposed asynchronous processing module consists of 24 MOS transistors and occupies $5.5 \mu{\rm m}\times 7.4 \mu{\rm m}$ area. Such array can be used as a co-processing unit aiding global binary image processing in standard pixel-parallel SIMD architectures in vision chips.

Application of the device of slices for automation of matrix calculations

The basic concepts of the device of slices for the processing of multidimensional numerical arrays are represented. The data on the developed matrix component supporting the concept of simple and generalized slices are given. The application efficiency of the slicing device and matrix components in industrial automation at the stages of matrix computation automation is shown.