Abstract
The ATLAS Level-1 Muon Barrel Trigger is one of the main elements of the first stage of event selection of the ATLAS experiment at the Large Hadron Collider. The challenge of the Level-1 system is a reduction of the event rate from a collision rate of 40 MHz by a factor 103, using simple algorithms that can be executed in highly parallel custom electronics with a latency of the order of 1 μs. The input stage of the Level-1 Muon consists of an array of processors receiving the full granularity of data from a dedicated detector (Resistive Plate Chambers in the Barrel). This first stage of the algorithm is performed directly on-detector, while the final stage is performed in boards mounted in the counting room, by the so-called off-detector electronics. The trigger algorithm is executed within a fixed latency, its real-time output is the multiplicity of muon candidates passing a set of programmable pT thresholds, and their topological information. The detector system and the trigger electronics are designed to achieve a safe bunch-crossing identification. In order to optimize design effort and cost, the trigger system integrates also the readout of the detector, with its own requirements on time resolution and overall data bandwidth. We present the detailed functional requirements of the Level-1 Muon Barrel system, its architecture, implementation and construction.
Highlights
Overview of the ATLAS Trigger SystemThe ATLAS Trigger system is designed to perform event selection and data rate reduction, from 40 MHz to O(100 Hz) via three different trigger levels [1]
A constraint of the system is the maximum fixed latency allowance of 2.5 μs, including processing time and propagation delays, coming from the need to store detector data on front-end electronics during the trigger decision. To achieve these goals ATLAS has chosen a design based on dedicated hardware systems, including a Central Trigger Processor (CTP) which takes the final decision starting from information coming from the Calorimeter and Muon detectors
Using as origin the nominal position of the p-p interaction region, the strip hit in the central plane of the Middle Station (RPC2) defines for low transverse momentum particles a coincidence window where to search for a correlated hit in the inner plane (RPC1) of the same Station
Summary
The ATLAS Trigger system is designed to perform event selection and data rate reduction, from 40 MHz to O(100 Hz) via three different trigger levels [1]. The algorithms used are capable of a rate reduction down to an overall acceptance rate of about 100 kHz. A constraint of the system is the maximum fixed latency allowance of 2.5 μs, including processing time and propagation delays, coming from the need to store detector data on front-end electronics during the trigger decision. A constraint of the system is the maximum fixed latency allowance of 2.5 μs, including processing time and propagation delays, coming from the need to store detector data on front-end electronics during the trigger decision To achieve these goals ATLAS has chosen a design based on dedicated hardware systems, including a Central Trigger Processor (CTP) which takes the final decision starting from information coming from the Calorimeter and Muon detectors. The Level trigger decision is fed-back to the front-end electronics and other readout components via the Timing, Trigger and Control System (TTC), based on a tree of optical and copper timing signal distribution boards and links
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