Process, Voltage And Temperature Variations Research Articles

Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 nm CMOS technology for the PLL application

This article introduces a novel approach of hybrid current-starved ring voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications. In this, two novel VCO designs are proposed. The first design is the current starved pull-up sleepy ring VCO which offers improved frequency of oscillation and reduced phase noise. The second design utilizes a hybrid current starved ring VCO with the bulk-driven keeper technique which yields better results by reducing the power consumption and mitigating leakage current. The proposed circuit is analysed with various process corners and performs parametric analysis and Monte-Carlo analysis to verify the robustness of the circuit using Cadence Virtuoso tool with 45 nm gpdk library. The average power of the proposed −2 circuit is 7.38 µW, and it achieves an oscillation frequency of 6.965 GHz at 1 V supply. It has low phase noise of −121.49dBc/Hz at 1 MHz, and the output noise of −166.42 dB. The obtained figure of merit (FOM) is −185.95dBc/Hz. The proposed design exhibits a frequency tuning range of 92.8 %. The results clearly demonstrate that the proposed design is extremely tolerant to PVT (process, voltage, and temperature) variations making it well suitable for high-frequency PLL applications.

Performance Comparison for FinFET Nanoscale Static and Domino Logic Circuits

The future prospects of complementary metal oxide semiconductor (CMOS) technology are estimated to be replaced by fin-shaped field effect transistor (FinFET) owing to its strong channel control, high driving capability and ease of fabrication. This paper envisages the effects of voltage, temperature and fin variation on power dissipation and delay for static and domino logic circuits. Circuit behavior becomes unpredictable due to process, voltage and temperature (PVT) variations such as irregular power consumption and performance deviation. It also accelerates circuit deterioration and makes them ineffective. The important circuit level leakage power reduction techniques like LCNT, LECTOR and INDEP have been applied to basic gates, 3-bit carry look ahead adder (CLA) and domino logic circuits at 16 nm FinFET technology. It is found that power delay product (PDP) in CLA using INDEP technique exhibits 61.48% less than conventional CLA. Leakage power reduction techniques have also been verified for the footer domino logic (FDL) circuit and performed Monte Carlo simulations for 10000 samples for reliability analysis. INDEP circuits are robust to PVT variations. The simulations have been completed using Cadence Virtuoso tool.

Design of ternary encoder and decoder using CNTFET

ABSTRACT Ternary logic emerges as an alternative to the conventional binary logic in designing high performance, energy-efficient VLSI circuits because it reduces the number of interconnects and chip area. In this paper, we presented low power and high speed 9:2 encoder and 2:9 decoder designs based on ternary logic using carbon nanotube field effect transistors (CNTFETs). These circuits have been extensively simulated at 32 nm CNTFET technology at 0.9 V power supply voltage. The ternary decoder has a power delay product (PDP) of 24.62 aJ and the ternary encoder has a PDP of 133 aJ for a given load. In the proposed designs, the chirality of the carbon nanotube (CNT) is varied to control the threshold voltage. The designs have been analysed with process, voltage and temperature (PVT) variations and it is shown that with PVT variations the performance of the designs vary marginally.

Integral impact of PVT variation with NBTI degradation on dynamic and static SRAM performance metrics

ABSTRACT Advanced CMOS technology is highly susceptible to ageing effects such as negative bias temperature instability (NBTI) and process variability. This article focuses on investigating the ‘combined impact’ of NBTI degradation along with the process, voltage and temperature (PVT) variations on SRAM metrics. These issues impact the performance of SRAM (Static Random Access Memory) cell in many ways but the two main dynamic metrics are critical read-stability and write-ability. The dynamic metrics can, in turn, be characterised by their static metrics, that determine the static noise margins (SNM) of SRAM. The dynamic metrics were analysed for symmetric and asymmetric NBTI degradation of two inverters of SRAM. NBTI degradations were incorporated on the pull-up transistors of SRAM cell. Furthermore, results of the correlated performance metrics are presented for varied data storage patterns in SRAM cell over its lifetime. This analysis aims to provide an insight into the effects of integrated PVT and NBTI degradation on SRAM cell performance, enabling robust designs and help designers at the early stage of design to mitigate system failure.

Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS

With technology scaling, stability, power dissipation, and device variability, the impact of process, voltage and temperature (PVT) variations has become dominant for static random access memory (SRAM) analysis for productivity and failure. In this paper, ten-transistors (10T) and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors (FGMOS). Power centric parameters viz. read power, write power, hold power and delay are the performance analysis metrics. Further, the stochastic parameter variation to study the variability tolerance of the redesigned cell, PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell. Stability has been illustrated with the conventional butterfly method giving read static noise margin (RSNM) and write static noise margin (WSNM) metrics for read stability and write ability, respectively. A comparative analysis with standard six-transistor SRAM cell is carried out. HSPICE simulative analysis has been carried out for 32[Formula: see text]nm technology node. The redesigned FGMOS SRAM cells provide improved performance. Also, these are robust and reliability efficient with comparable stability.

Ultra-low-power wideband NMOS LC-VCO design for autonomous connected objects

In this paper, a fully integrated sub threshold LC voltage controlled oscillator (VCO) is presented. A design methodology is also proposed to find the optimal parameters lowering the power consumption. This methodology has been applied to design oscillators for different frequency bands. Furthermore, an adaptive body biasing technique has been used to improve the startup constrains and allows a high immunity to PVT (process, voltage and temperature) variations. A VCO operating in 5 GHz ISM (Industrial, Scientific and Medical) band has been realized with the proposed methodology in 0.13 μm CMOS. It consumes only 468 μW from 0.39 V supply voltage. This makes it possible to meet the required specifications of autonomous connected objects and IoT applications. The measured oscillation frequency can be tuned from 5.14 to 5.44 GHz. The obtained phase noise is approximately equal to − 112 dBc/Hz in post-layout simulation (PLS) and − 104.5 dBc/Hz in measure.

A sub-harmonic injection locking clock multiplier with FLL PVT calibrator

Using the sub-harmonic injection locking technique, an enhanced differential Digitally Controlled Ring Oscillator (DCRO) with improved phase noise performance is proposed in this paper. All circuit blocks were implemented using digital design flow and designed using a hardware description language. A Frequency Locked Loop-based Process, Voltage and Temperature (PVT) calibrator was utilized to overcome PVT variations. The design was fabricated in 65 nm CMOS technology and its area is 0.017 mm2. The measured phase noise at 1 MHz offset and RMS jitter are −128 dB/Hz and 197fs, respectively. The design was tested in the presence of voltage and temperature variations. The maximum jitter difference percentage is 13.7% at 70 °C and 1.1 V and the phase noise value changes by a maximum of 0.7 dB over the whole range of voltages and temperatures. Furthermore, when the design was tested in the presence of switching noise, it provides up to 7 dB improvement in phase noise when compared to a single ended version of the DCRO.

Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier

The folded cascode operational amplifier (FCOA) designed in this paper is the single-pole operational amplifier (op amp). In this design, the conventional current mirror is replaced with wide swing current mirror to overcome the essential drawback of cascode configuration. In this paper, negative feedback is used to improve the small-signal gain and to ensure better stability than multistage amplifiers. This paper also aims at improving the output voltage swing, power dissipation and robustness of the op amp. The designed FCOA is proficient in achieving 67.44dB gain and 1.77V output swingat typical voltage for 180nm CMOS technology. The FCOA is highly stable with phase margin of 62.58º while dissipating 0.5mW power. This amplifier is further verified for variability analysis for Process, Voltage and Temperature (PVT) variations to check robustness. All together testing is done at 45 different PVT combinations and results are tabulated accordingly. At each corner temperature and voltage are varied for all together nine combinations to properly address the effect of PVT variations. The results shows that the op amp exhibits desired response at four corners (FF, TT, SS, and FS) of process, over -40º to 125º C temperature range. Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation. Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.

OCTAN: An On-Chip Training Algorithm for Memristive Neuromorphic Circuits

In this paper, we propose a hardware friendly On-Chip Training Algorithm for the memristive Neuromorphic circuits (OCTAN). Although the proposed algorithm has a simple hardware like that of the random weight change (RWC) algorithm, it is much more efficient in terms of convergence speed and accuracy. In this algorithm, weights of the circuit are updated individually by a small value and the effect of individual weight update is assessed. If the weight change causes an increase in the error of the network, the weight update is reversed by applying the same change in the reverse direction twice. The usefulness of the proposed algorithm is verified by training some neuromorphic circuits for different applications. Compared to RWC and stochastic least-mean-squares (SLMS) training algorithms, our proposed algorithm needs, on average, $329\times $ fewer epochs to find the minimum error point. Moreover, the accuracy of the networks trained by OCTAN is, on average, about 46% higher than those of RWC and SLMS algorithms. Additionally, a hardware for OCTAN is presented. This hardware provides a speedup of $172\times $ ( $61\times $ ) compared to that of the RWC (SLMS) algorithm. Finally, the impact of PVT (process, voltage, and temperature) variations is studied on the proposed training hardware indicating an average training error increase of less than 3.27% in the presence of variations.

A RF PVT Compensated Negative Resistance Circuit for Q-factor Improvement of Passive Elements in CMOS

A RF process, voltage and temperature (PVT) compensated negative resistance (NR) circuit is proposed to improve the quality factor (Q-factor) of CMOS passive devices while ensuring stability over PVT variations. It is implemented in the form of a grounded NR circuit to support single-ended RF circuit applications. Various circuit techniques such as a diode-connected load, a proportional-to-absolutetemperature (PTAT) current source and an adaptive body-biasing based threshold voltage compensation have been adopted to obtain a stable negative resistance value. Simulation results show that the Qfactor of on-chip spiral inductors loaded by the proposed NR circuit is improved from 6 to 60 at 1 ㎓ under typical corner conditions (tt, 1.2V, 27 ℃). The simulated Q-factor variation in corner conditions is approximately 37, which is approximately 6.5 times more stable than conventional NR circuit without compensation.

A high-precision current-mode multifunction analog cell suitable for computational signal processing

In this paper, a high linear, low-voltage two-quadrant current squarer as multifunction analog cell, is presented. To implement the squarer circuit, translinear loops with matched NMOS transistors operating in weak inversion region are used. The proposed cell is used as a basic building block for current-mode computational analog functions such as rectifier (absolute-value), multi-input vector summation and exponential function generator. We perform post-layout plus Monte Carlo simulations of the presented functions with 0.18 μm (level-49 parameters) TSMC CMOS technology that prove their superiority over some other advanced works and robustness against PVT (process, voltage and temperature) variations.

An up-down topology based-current mode adjustable-gain square-rooting/geometric-mean circuit

A high speed low power current-mode square-rooting/geometric-mean circuit is presented in this paper. The up-down topology with MOS translinear loop in sub-threshold is the basic building block of the proposed circuit which leads to lower supply voltage requirement and body effect issues. This design is also helpful to implement the square-rooting operation of a signal and geometric-mean of two variable signals both with adjustable gain. The performance has been simulated using HSPICE software in 0.18 µm TSMC (level-49 parameters) CMOS technology. Post-layout simulation results with 1-V DC supply voltage show that the maximum linearity error of 1.3%, the − 3 dB bandwidth of 21.9 MHz and maximum power consumption of 700 nW are granted. Monte Carlo analysis is also performed to ensure the stability and robustness of the circuit’s performance in the presence of the PVT (process, voltage and temperature) variations.

High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology

In this paper, we propose a novel high reliability and low cost DNU (Double Node Upset) tolerant latch, HRCE (High Robust and Cost Effective) latch, for nanoscale CMOS technology. In the presence of the interlocked feedback loop composed of C-elements and inverters, the proposed latch design can self-recover from the DNU. The proposed latch is evaluated and compared to previous soft error (SE) tolerant latches, and SPICE simulations are carried out with SMIC 65 nm technology model. Simulation results indicated that our proposed latch saves approximately 84.5% APDP (Area-Power-Delay Product) on average with the lowest APDP. Besides, we investigated the PVT (process, voltage and temperature) variations effects on the HRCE latch and other hardened latches, and the results indicated that the HRCE latch has less sensitivity towards process variation.

Optimization and CMOS design of chaotic oscillators robust to PVT variations: INVITED

Edward Lorenz was an early pioneer of the chaos theory. He discovered that small changes in initial conditions produce large changes in long-term outcome, and introduced a chaotic attractor already known as Lorenz chaotic oscillator, which produces a butterfly-like behavior. This and all kinds of continuous-time chaotic oscillators can be simulated with different numerical methods. However, a bad choice of the step size and/or parameters of the mathematical models can produce errors or even mitigate the chaotic behavior. These issues are related to the main property of chaotic oscillators, the high sensitivity to the initial conditions, which is quantified by evaluating the maximum Lyapunov exponent (MLE). The Lorenz and other representative oscillators like Lü, Chua's circuit and Rössler have been implemented using different discrete electronic devices and few ones with integrated circuits (IC) using CMOS technologies. Designing CMOS chaotic oscillators is challenging because a very small variation in their parameters from their mathematical models or in the sizes of the MOS transistors may suppress the chaotic behavior. This article describes how to perform a successful simulation and optimization, and how to synthesize the mathematical models using CMOS technology. The application of metaheuristics to optimize MLE by varying the parameters of the oscillators, and the optimization of the CMOS IC design to guarantee robustness to process, voltage and temperature (PVT) variations, are discussed. Finally, we discuss issues on the application of chaos generators in random number generators, robotics and chaotic secure communication systems.

A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS

Adaptive voltage frequency scaling (AVFS) techniques based on in-situ timing monitoring can mitigate the excessive timing margin caused by process, voltage and temperature (PVT) variations. However, they usually adjust the frequency by clock gating, clock half-division, or phase locked loop configuration, which cause large performance loss or need a long lock time. Thus, a compact structured adaptive clock stretching circuit is proposed here for very rapid frequency adjustment. It is very useful for AVFS systems by stretching the clock cycle with only within-a-cycle response time. The proposed architecture generates multi-phase clocks through a series of delay elements and continuously picks an appropriate phase clock to form a stretched clock. It also uses a process voltage temperature monitor to adjust the phase clock selection and makes this circuit suitable under PVT variations. Fabricated in 40-nm CMOS process, it only occupies a core area of 85* <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$83~{\mu }\text{m}^{2}$ </tex-math></inline-formula> . Measurements show that it can stretch the clock cycle immediately upon the stretch signal with within-a-cycle response time. It has a wide voltage range from 0.43 V to 1.1 V, with power consumptions of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$38.2~{\mu }\text{W}$ </tex-math></inline-formula> at 0.43 V/10 MHz and 4.55 mW at 1.1 V/1.2 GHz. Plus, it can provide configurable stretch amounts for the AVFS system. Thus, it can provide a within-a-cycle, low overhead frequency adjustment solution for AVFS systems.

PVT compensated inverter‐based OTA for low‐voltage CT sigma‐delta modulators

An inverter-based operational transconductance amplifier (OTA) robust to process, voltage and temperature (PVT) variations is proposed in this Letter to enable the design of low-voltage power-efficient continuous-time sigma-delta modulators (CT-SDMs). The proposed OTA significantly reduces the unity gain-bandwidth variation across PVT corners while presenting a DC gain of 41.9 dB at nominal conditions when operated at 0.6 V. The effectiveness of the proposed circuit was verified in a 180 nm CMOS process by transistor-level simulations including PVT variations and mismatch. Also, a 0.6 V third-order CT-SDM is designed to verify the robustness against voltage and temperature variations.

Effect of PVT variations on differential-time signaling data link architecture

In this paper, the effect of process, voltage and temperature (PVT) variation on the differential-time signaling (DTS) serial link architecture has been studied. An example of 65 nm CMOS 4-bit 6 Gb/s DTS serial link has been designed and simulated using 1.5 GHz as an input clock signal in order to study the effect of PVT variation on DTS architectures. Mont-Carlo simulations have been carried out for the designed link. The simulated link has been tested under different operating temperatures from 0 to 120 °C, the link achieves correct transmission for the temperature range from 0 to 80 °C without calibrating the delay lines against the temperature change. The voltage supply has been varied from 0.95 to 1.05 V in order to study the effect of the voltage supply variation. The simulated link achieves correct transmission for a voltage supply variation within ± 2.5% of the nominal value without calibrating the delay lines against the voltage supply change. Using the DTS architecture as a serial link tolerate an adequate amount of PVT variation as well as relaxes the design constrains of the calibration technique, which is required for the delay lines to ensure correct transmission.

Design of multiple-valued logic gates using gate-diffusion input for image processing applications

In this work, unique characteristics of carbon nano-tube field effect transistor (CNTFET) are used to propose a universal cell with a simple architecture based on the binary modified gate-diffusion input (m-GDI) method for designing fundamental gates in the voltage-mode multiple-valued logic (MVL) with any arbitrary number of logic levels for processing at nano-scales. The results of the simulations confirm more energy-efficiency, larger noise margins and lower sensitivity of the proposed designs in different logic levels as compared with the state-of-the-art designs. The effects of the process, voltage and temperature (PVT) variations are extensively evaluated by Monte–Carlo simulation. According to the results, the proposed designs are robust against PVT variations and noise. The proposed structure is applied to the MVL-based image processing. The results show that the output images of the proposed MVL-based inexact gates have an appropriate quality in compare with the images generated by the other similar exact gates.

A fully integrated and high precision 350 mV amplitude regulated LVDS transmitter compensating PVT variations

A low cost solution and high precision output amplitude regulation for Low-Voltage Differential Signaling (LVDS) driver targeted for TIA/EIA-644-A standard is reported. The proposed architecture has high tolerance towards internal resistors variations by adapting continuous calibration of output amplitude through a negative-feedback loop. It eliminates the requirements of high precision or expensive external resistor or post-fabrication calibration. Fabricated in 0.13-μm CMOS with a supply voltage of 3.3 V, the prototype exhibits regulated 700 mV output amplitude which is able to compensate for process, voltage and temperature (PVT) variations.

Low-Power High-Speed Analog Multiplier/Divider Based on a New Current Squarer Circuit

In this paper, a CMOS ultra-low-power, high-speed four-quadrant current multiplier/divider circuit is presented. Based on square-difference approach, the proposed circuit is using a new current squarer with MOS transistors operating in weak inversion region. The translinear loops are the basic building blocks in realization of the current-mode two-quadrant squarer and four-quadrant multiplier/divider circuits. The proposed designs have been simulated using HSPICE in 0.18 $$\upmu \hbox {m}$$ TSMC CMOS (level-49 parameter) process. Post-layout simulation results with 0.8 V power supply show the total power dissipation of 770 nW, the total harmonic distortion of 0.67% (at 100 kHz), the maximum linearity error of 2%, and the − 3 dB bandwidth of 34.1 MHz. Monte Carlo analysis is also performed to ensure the stability and robustness of the circuit’s performance in the presence of the PVT (process, voltage, and temperature) variations.