Abstract
The folded cascode operational amplifier (FCOA) designed in this paper is the single-pole operational amplifier (op amp). In this design, the conventional current mirror is replaced with wide swing current mirror to overcome the essential drawback of cascode configuration. In this paper, negative feedback is used to improve the small-signal gain and to ensure better stability than multistage amplifiers. This paper also aims at improving the output voltage swing, power dissipation and robustness of the op amp. The designed FCOA is proficient in achieving 67.44dB gain and 1.77V output swingat typical voltage for 180nm CMOS technology. The FCOA is highly stable with phase margin of 62.58º while dissipating 0.5mW power. This amplifier is further verified for variability analysis for Process, Voltage and Temperature (PVT) variations to check robustness. All together testing is done at 45 different PVT combinations and results are tabulated accordingly. At each corner temperature and voltage are varied for all together nine combinations to properly address the effect of PVT variations. The results shows that the op amp exhibits desired response at four corners (FF, TT, SS, and FS) of process, over -40º to 125º C temperature range. Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation. Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.
Highlights
Complementary Metal Oxide Semiconductor (CMOS) technology has dominated the VLSI market since last fifty to sixty years
Corner analysis results of designed folded cascode op amp (FCOA) at 130nm are presented for FF, TT, Slow NMOS-PMOS (SS), FS and SF corners for different values of supply voltage as Maximum (Vmax), Typical (Typ), Minimum (Vmin) at different temperatures as Minimum (-40°C), Typical (25°C) and Maximum (125°C)
In this paper, Folded Cascode CMOS Op Amp is implemented at 180nm and 130nm using Mentor Graphics
Summary
Complementary Metal Oxide Semiconductor (CMOS) technology has dominated the VLSI market since last fifty to sixty years. CMOS transistors are scaled regularly in accordance with Moore’s law to achieve significant performance as per various tradeoffs like area, speed, power and design requirements. The transistor dimensions have reached to nanometer level. Due to this various adverse phenomenon like leakage currents are dominating over the desired performance on the verge of very deep submicron technology. This has an impact on power dissipation and variability of the circuits. There has been tremendous work carried by researchers in digital domain to improve upon this
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