Process Design Kit Research Articles

Expanded Noise Margin 10T SRAM Cell using Finfet Device

Static random access memory (SRAM) cells are being improved in order to increase resistance to device level changes and satisfy the requirements of low-power applications. A unique 10-transistor FinFET-based SRAM cell with single-ended read and differential write functionality is presented in this study. This cutting-edge architecture is more power-efficient than ST (Schmitt trigger) 10T or traditional 6T SRAM cells, using only 1.87 and 1.6 units of power respectively during read operations. The efficiency is attributable to a lower read activity factor, which saves electricity. The read static noise margin (RSNM) and write static noise margin (WSNM) of the proposed 10T SRAM cell show notable improvements over the 6T SRAM cell, increasing by 1.67 and 1.86, respectively. Additionally, compared to the 6T SRAM cell, the read access time has been significantly reduced by 1.96 seconds. Utilising the Cadence Virtuoso tool and an 18nm Advanced Node Process Design Kit (PDK) technology file, the design's efficacy has been confirmed. For low-power electronic systems and next-generation memory applications, this exciting 10T SRAM cell has a lot of potential.

(Invited) Cryogenic Electronics for Quantum Computing ICs: What Can Bring FDSOI

To design efficient quantum computers, conventional electronics is required as close as possible to the quantum bit (qubit) devices, considering either superconducting or Si-spin qubits, for the read-out and control, thus reducing the need for wiring toward room temperature [1]. This need highlights the broad importance of exploring and developing low-temperature CMOS technologies, with operation temperatures ranging from 4.2K down to well below 1K. Moreover, the Si-spin qubit process is also compatible with the CMOS process, allowing both of them, in principle, to be monolithically integrated on a single chip [2], [3]. This could provide an essential building block for any large-scale quantum processors, by enabling the design of scalable close-to-qubit cryogenic electronics for massive qubit matrix indexation and, ultimately, development of fault-tolerant universal gate-based quantum computers [4].In this approach, FDSOI technologies appear as a valuable solution, with their unique property of being able to adjust its threshold voltage (Vth) as a function of the temperature by the mean of a back bias VB. FDSOI thus enables high performance and low-power electronics. However, there is currently no process design kit to design CMOS circuits at cryogenic temperature, whatever the technology node considered. Therefore, extensive electrical characterization is required, with the aim of building a future cryogenic compact model, or at least of providing analytical and physics based models to designers in order to help them to optimize their circuits [5].In this work, we present an overview of the performances of FDSOI CMOS technology down to deep cryogenic temperature, with specific attention to devices electrostatics, variability or thermal effects. Because these aspects are essential for the development of compact models and robust design tools, we present recent progresses in electrical characterization and analysis of FDSOI MOSFETs down to 100mK, and the underlying physics, highlighting the effect of the back bias VB.We show that transistors can fully operate down to 100mK, keeping the same efficiency of the back bias on the threshold voltage [6]. Overall performances are mostly improved at low temperature, with e.g. a high reduction of the subthreshold slope and of the off current, or a higher transconductance maximum value due to higher carrier mobility. The tunability of the threshold voltage on a wide range through the back-bias offers a great advantage to the FDSOI technology, allowing improved performances [7] and the optimization of circuit in cryogenic environment [8], [9]. Other important electrical characteristics have also been investigated down to very low temperature, such as variability and mismatch properties [7], [10], or low frequency noise [11]. As a result, we show that FDSOI technology can outperform other CMOS technologies in cryogenic operation.Thermal effects, which play a fundamental role in cryogenic electronics – operating at various temperature stages, with limited cooling power. The study of self-heating effects at cryogenic temperature in this regard provides valuable information on how to manage thermal effects, and is discussed [7], [15].Finally, modeling issues are also addressed. Besides serious numerical difficulties due to singularities appearing at low temperature when solving model equations, the change of important physical parameters (like carrier mobility, thermal conductivity,...) needs to be correctly taken into account in future compact or analytical models. In addition, new physical effects evidenced at low temperature also need to be understood, analytically modeled and included as well. In particular, transport exhibits evidence of strong intersubband scattering in the channel of thin film FDSOI transistors [12]. The equations describing the sub-threshold regime are also strongly modified [13], [14].[1] E. Charbon et al., IEDM, 2016.[2] P. Galy et al., IEEE J. Electron Devices Soc., 2018.[3] L. Le Guevel et al., Appl. Phys. Rev., 2020.[4] X. Xue et al., Nature, 2021.[5] C. Enz et al., EDM, 2020[6] B. Cardoso Paz et al., EUROSOI-ULIS, 2020.[7] M. Cassé et al., to be published in IEDM, 2022.[8] H. Bohuslavskyi et al., IEEE Trans. Electron Devices, 2018.[9] L. Le Guevel et al., ISSCC, 2020.[10] B. Cardoso Paz et al., VLSI, 2020.[11] B. Cardoso Paz et al., IEEE Trans. Electron Devices, 2020.[12] M. Cassé et al., Appl. Phys. Lett., 2020.[13] H. Bohuslavskyi et al., IEEE Electron Device Lett., 2019.[14] G. Ghibaudo et al., Solid. State. Electron., 2020.[15] K. Triantopoulos et al., IEEE Trans. Electron Devices, 2019.

A high‐speed and low‐latency hardware implementation of RC4 cryptographic algorithm

AbstractIn this letter, a high‐speed and low‐latency Ron Rivest‐4 (RC4) encryption algorithm is designed based on SMIC 14 nm process. Since the key issue of limiting the throughput of RC4 encryption algorithm is the swapping operation of S‐box, this proposed design is capable of achieving four swapping operations of S‐box within a clock cycle by utilizing fully combinational logic designs and advanced computations. All 256 swapping operations of key scheduling algorithm (KSA) can be done in 64 clock cycles. Moreover, the novel design greatly improves the encryption efficiency of RC4 since each clock cycle offers 4 bytes of key stream. The whole area can be further optimized by reusing the existing modules, and a lightweight countermeasure is embedded into the RC4 design to break the correlation between the processed data and power dissipation against differential power analysis (DPA) attacks. Finally, the whole design is assessed by the SMIC 14 nm process design kits (PDK). The corresponding clock frequency, throughput, area, and latency, respectively, are achieved as 1 GHz, 32 Gbps, 51,596 m2, and 74 clock cycles.

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage (Vth) of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time (t). A device-level approach for Vth degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of t. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre-and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with t to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre-and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in Eldo SPICE environment with 65 nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.

On noise-induced transient bit flips in subthreshold SRAM

We propose a rigorous SPICE simulation framework, compatible with industrial process design kits, to observe transient bit flips in CMOS SRAM due to the intrinsic transistor noise. The parameters of transient noise simulation are selected according to the noise behaviour and bandwidth of the inverter, however under CPU-time constraint. The methodology is illustrated in 28nm FD-SOI technology. We study the combined effects of the random telegraph noise, flicker and thermal noise sources, for the first time to our knowledge. The extracted mean times to failure (MTTF) are compared to those reported in the literature in extreme voltage, temperature and variability conditions. The MTTF spans from below 0.1ms to 108s, following a theoretical trend logMTTF∝VDD2.

CMOS Linear Laser Driver for Intermediate Frequency over Fiber (IFoF) Links

The main objective of the proposed linear laser driver (LLD) is to reduce signal distortion in an analog direct modulation laser configuration used for intermediate frequency over fiber links. This work draws on an open-loop configuration featuring two differential pair blocks in a cascade arrangement to achieve a bandwidth measurement of 415 MHz at the half-power point, a total harmonic distortion of 4.57% for a fundamental frequency of 100 MHz, and an amplitude of 100 mVpp. The LLD provides a gain of 12.3 dB for a differential output and an output impedance of 46 Ω. The design, layout, and integration correspond to the process design kit for TSMC 65-nm CMOS technology. Experimental results show the advantage over other previously reported laser drivers.

Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems

This paper presents estimation and analysis of the higher order harmonics, power features, and real performance of flip-flop and master-slave latch topologies. This research article outlines the impact of transistor model quality and input signal selection on the estimate of higher order harmonic contents of switching waveform emitted by the digital integrated circuits. Highly integrated systems require accurate estimation of higher order harmonics to control noise. This work presents simulations of 12 kinds of flip-flop and latch topologies on different process technologies i.e., 28 nm, 45 nm, 65 nm, and 130 nm. It is implied that the steeper the spectrum roll-off, the fewer the contents of higher order harmonics. Results of 28 nm process design kit are improved compared to 45 nm, 65 nm, and 130 nm process design kits. Furthermore, the results of the comparison of representative flip-flop and latch topologies illustrate the advantage of the approach and the suitability for high performance and low power consumption.

A genetic‐algorithm‐based synthesis of microwave integrated distributed amplifiers

AbstractThis article presents a genetic algorithm‐based technique for microwave integrated distributed amplifier synthesis. To speed‐up synthesis, only linear characteristics are used in the goal function. The technique uses MMIC foundry process design kit models providing manufacturing‐ready schematics to be found. The models from the process design kit are presented as S‐parameters again to enhance algorithm performance. The technique allows searching among most of the existing schematics of the microwave distributed amplifier but is not limited to typical topologies. The section number is theoretically unlimited and makes it possible to find principally new circuit topology. The synthesis shortens and simplifies the distributed amplifier design time. Experimental validation of the technique is carried out by synthesizing the broadband driver stage for the 20–30 GHz buffer amplifier. The technique produces several amplifier topologies meeting the requirements. The most appropriate circuit was manufactured using a commercial 0.25 μm GaAs pHEMT process. The manufactured buffer amplifier demonstrates a gain of 10 dB and 20 dBm output power at a 1 dB compression point.

Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse

Spiking neural networks (SNNs) implemented in neuromorphic computing architectures promise a high degree of bio-plausibility and energy efficiency compared to the artificial neural network (ANN). Thus, SNN-based spiking associative memories are preferred for high capacity, area, and energy-efficient neural associative memories (NAMs). While most previously published works focused on ANN-based NAM, this work implements the full CMOS circuit of memristor crossbar-based spiking NAM for the first time. Instead of using any software-based memristive SPICE model or memristive devices that are yet not available in standard CMOS technology process design kits (PDKs), in our work, the CMOS-based memristive synapse circuit is employed to address practical circuit implementation challenges. The complete on-chip learning of the system is demonstrated using the bio-plausible spike-timing-dependent plasticity (STDP) learning mechanism without employing any external coprocessor, e.g., microprocessor, field-programmable gate array (FPGA). The entire system is implemented at the transistor level using 180-nm standard CMOS technology to demonstrate the pattern recognition application. The robustness of the proposed circuit is also evaluated to demonstrate the tolerance against the CMOS fabrication non-idealities.

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

Traditional von Neumann architecture bottlenecks such as the “memory wall” limit artificial intelligence (AI) development, and in-memory computing (IMC) as a new computing architecture can solve the above problems. Spin-orbit-torque-magnetic random access memory (SOT-MRAM) has very good advantages in IMC architecture because of its good compatibility with CMOS, high tunneling magnetoresistance (TMR) ratio, and high energy efficiency. In this paper, we propose a 6T-3M-based MRAM-IMC architecture with reconfigurable memory mode and logical operation mode. The functionality of the proposed architecture is validated using the 28 nm process design kit and the SOT-MTJ model.

A Comprehensive Modeling Platform for Interconnect Technologies

With device scaling facing major physical and manufacturing challenges, many research efforts have been focused on the impact of device parameters and designs on circuit performance and power dissipation. However, similar research on the impact of Cu-low <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> interconnects at the advanced nodes and the potential benefits offered by novel wire and via material and process options is lacking. While studies based on smaller circuit blocks exist, the exploration of these benefits for the performance of larger processors is lacking although the limits imposed by interconnect resistances become more severe due to longer wires and increased complexity in larger circuits. In this article, we conduct a study to quantify the effect of back-end-of-the-line (BEOL) technology improvements on circuit power, performance, and area (PPA) of various circuits from small blocks up to a full commercial processor with L1-cache. We modified the interconnect technology (ICT) files for the ASAP7 process design kit (PDK) to reflect various BEOL options such as thinner barrier/liners, near barrierless vias, and alternative material options based on TCAD simulations. We show that these options can offer up to a 1.769 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> improvement in effective frequency or up to three metal-level savings.

Design of Hybrid Beamforming System Based on Practical Circuit Parameter of 6-Bit Millimeter-Wave Phase Shifters

This paper addresses the design of a hybrid beamforming system considering the circuit parameter of six-bit millimeter-wave phase shifters based on the process design kit. The phase shifter design adopts 45 nm CMOS silicon on insulator (SOI) technology at 28-GHz. Various circuit topologies are utilized, and in particular, a design is presented based on switched LC components, connected in a cascode manner. The phase shifter configuration is connected in a cascading manner to get the 6-bit phase controls. Six different phase shifters are obtained, which are 180°, 90°, 45°, 22.5°, 11.25°, and 5.6°, with a minimum number of LC components. The circuit parameters of the designed phase shifters are then incorporated in a simulation model of hybrid beamforming for a multiuser MIMO system. The number of OFDM data symbols used in the simulation is ten for eight users, 16 QAM modulation schemes, −25 dB SNR, 120 simulation runs, and around 170 h runtime. Simulation results are obtained considering four and eight users, assuming accurate technology-based models of RFIC components of the phase shifter as well as ideal phase shifter parameters. The results indicate that the performance of the multiuser MIMO system is affected by the accuracy level of the phase shifter RF component models. The outcomes also reveal the performance tradeoff based on user data streams and the number of BS antennas. By optimizing the amount of parallel data streams per user, higher data transmission rates are achieved, while maintaining acceptable error vector magnitude (EVM) values. In addition, stochastic analysis is conducted to investigate the distribution of the RMS EVM. The outcomes show that the best fitting of RMS EVM distribution of the actual and ideal phase shifters agreed with the log-logistic and logistic distributions, respectively. The obtained (mean, variance) values of the actual phase shifters based on accurate library models are (46.997, 481.36), and for ideal components the values are (36.47, 10.44).

Wafer-scale heterogeneous integration of thin film lithium niobate on silicon-nitride photonic integrated circuits with low loss bonding interfaces.

Silicon nitride (Si3N4) is a versatile waveguide material platform for CMOS foundry-based photonic integrated circuits (PICs) with low loss and high-power handling. The range of applications enabled by this platform is significantly expanded with the addition of a material with large electro-optic and nonlinear coefficients such as lithium niobate. This work examines the heterogeneous integration of thin-film lithium-niobate (TFLN) on silicon-nitride PICs. Bonding approaches are evaluated based on the interface used (SiO2, Al2O3 and direct) to form hybrid waveguide structures. We demonstrate low losses in chip-scale bonded ring resonators of 0.4 dB/cm (intrinsic Q = 8.19 × 105). In addition, we are able to scale the process to demonstrate bonding of full 100-mm TFLN wafers to 200-mm Si3N4 PIC wafers with high layer transfer yield. This will enable future integration with foundry processing and process design kits (PDKs) for applications such as integrated microwave photonics and quantum photonics.

High-Speed Waveguide-Integrated Avalanche Photodiodes for Near-Infrared Wavelengths on SiN-on-SOI Photonic Platform

Recently, there have been efforts on developing monolithically integrated avalanche photodiodes (APDs) for visible and near-infrared (NIR) wavelengths. However, the fabrication of these detectors in commercial photonic foundries often requires custom integration flow due to many design rule violations in standard integration process. This increases the fabrication cost, hinders the use of highly robust integration platform, and prevents access to well-mature process design kits. Here, we report on waveguide-integrated APDs operating at 850 nm by utilizing a commercial silicon nitride-on-silicon-on-insulator (SiN-on-SOI) photonics platform with no process modifications. Our devices comprise a SiN waveguide for input light routing and an SOI layer underneath to form APDs. We examine the effect of different junction parameters and device length on DC and high-speed device performance. We demonstrate high gain-bandwidth product up to 120 GHz with low dark current of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{&lt; }$</tex-math></inline-formula> 25 nA and high responsivity that can reach 0.71 A/W, and observe open eye diagrams at up to 40 Gbps for all device variations. The performance parameters are on-par or even superior when compared to other integrated APDs operating in the NIR wavelengths. Being compatible with the standard integration flow of a multi-project wafer service of a commercial foundry, our devices are readily accessible, and they expand the functionalities of well-mature SiN-on-SOI photonics platform for applications ranging from optical interconnects, LIDAR, visible light communication to biosensing and quantum applications.

Novel FDNR, FDNC and lossy inductor simulators employing second generation voltage conveyor (VCII)

AbstractIn this research the second‐generation voltage conveyor (VCII) is employed in the design of grounded frequency dependent negative resistor (FDNR) and Frequency dependent negative conductance (FDNC). Additionally, two lossy parallel and series R‐L inductor simulators are also designed. To the best knowledge of the authors above mentioned immittance simulators are first time implemented using VCII. The FDNR requires two VCII, two capacitors and one grounded resistor. FDNC is implemented using three VCII, three resistors and two grounded capacitors. The R‐L inductor emulators requires two VCII, two resistors and one grounded capacitor. All the presented immittance simulators do not require any kind of passive component matching. The non‐ideal gain and sensitivity analysis is conducted to study their performance under circuit parameter variations. Parasitic analysis is also done for the FDNR, FDNC and R‐L inductance simulators to study the effect of parasitic impedance on the circuit operation. To validate the designs, they are simulated in Cadence design environment using 0.18 μm process design kit (PDK) at ±0.9 V supply. Additionally, the circuits are also validated using the macro model of commercially available integrated circuit (IC) AD844. The theoretical and simulation results are found to be in close agreement.

A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications

The work presented in this article focuses on designing a floating MOS-dynamic threshold voltage MOSFET (DTMOS)-based circuit to emulate a memristor. The proposed circuit consists of four transistors, including a DT-MOSFET and an external capacitor, which helps obtain high-frequency operations up to 3 MHz. This facilitates easier integration of the devices and monolithic IC fabrication. The correctness of the proposed emulator is validated by conducting various parametric analyses at different operating frequencies and process corners, and it generates acceptable pinched hysteresis loops (PHLs) at various frequencies. Furthermore, pre- and post-layout validation of the proposed emulator are also performed using Cadence Virtuoso with Taiwan Semiconductor Manufacturing Company (TSMC) 180-nm process design kits (PDKs) to prove its effectiveness as a memristor. The area and power consumption of the proposed emulator are <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$157.48~\mu \text {m}^{2}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.24~\mu \text {W}$ </tex-math></inline-formula> , respectively. The physical experiment of the proposed memristor emulator is performed using ALD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1106~n$ </tex-math></inline-formula> -channel MOSFETs to characterize its functionality as a real-life memristor. It is also used in designing a memristor-based application to showcase its applicability in power and area optimal circuit design.

Hadamard product-based in-memory computing design for floating point neural network training

Deep neural networks (DNNs) are one of the key fields of machine learning. It requires considerable computational resources for cognitive tasks. As a novel technology to perform computing inside/near memory units, in-memory computing (IMC) significantly improves computing efficiency by reducing the need for repetitive data transfer between the processing and memory units. However, prior IMC designs mainly focus on the acceleration for DNN inference. DNN training with the IMC hardware has rarely been proposed. The challenges lie in the requirement of DNN training for high precision (e.g. floating point (FP)) and various operations of tensors (e.g. inner and outer products). These challenges call for the IMC design with new features. This paper proposes a novel Hadamard product-based IMC design for FP DNN training. Our design consists of multiple compartments, which are the basic units for the matrix element-wise processing. We also develop BFloat16 post-processing circuits and fused adder trees, laying the foundation for IMC FP processing. Based on the proposed circuit scheme, we reformulate the back-propagation training algorithm for the convenience and efficiency of the IMC execution. The proposed design is implemented with commercial 28 nm technology process design kits and benchmarked with widely used neural networks. We model the influence of the circuit structural design parameters and provide an analysis framework for design space exploration. Our simulation validates that MobileNet training with the proposed IMC scheme saves in energy and in time versus the same task with NVIDIA GTX 3060 GPU. The proposed IMC design has a data density of 769.2 Kb mm−2 with the FP processing circuits included, showing a 3.5 × improvement than the prior FP IMC designs.

A low output ripple and high security on‐chip voltage regulation based on Fourier transform

SummaryIn modern integrated circuits (ICs), integrating workload‐agnostic multiphase switched‐capacitor (SC) voltage converters on‐chip is an effective way to reduce the transient response time, improve the security, and boost the power efficiency. However, a stochastic and unbalanced active sequence within the multiphase SC converter may undermine the corresponding output voltage ripple significantly. In this paper, a novel algorithm that is based on Fourier transform is capable of efficiently mitigating the amplitude of output ripple without compromising its security drastically. To achieve this objective, firstly, the output ripple of a single‐phase SC converter needs to be approximated with a Fourier expansion. Then the relationship between the output ripple and active phase sequence of a multiphase SC converter can be modeled precisely under the assistance of Fourier transform. After maximizing the randomness of the active sequences of the multiphase SC converter under different workload conditions and filtering a certain number of phase sequences with unsatisfied output ripples, the optimum control algorithm is generated. As shown in the result, the amplitude of output ripple of a multiphase SC converter can be reduced by 69.5% with negligible security loss and less than 29% power and area overhead under the 55 nm process design kits (PDK).

Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis

This work presents the comparison between Nanowire Tunnel Field-Effect Transistor (NW-TFET) and Line-TFET applied on the design of Low-Dropout Voltage Regulator (LDO). Both devices have a SiGe source composition in order to enhance the current drive. The transistors were modeled using lookup tables (LUTs) approach based on experimental data using Verilog-A language. The LDOs were designed for two conditions, considering different gm/ID, load currents and load capacitances. In order to compare the TFET LDOs with an established technology, a MOSFET LDO was designed with TSMC 0.18 µm process design kit. Both TFET LDOs reach stability without the presence of a compensation capacitor. For gm/ID = 10.5 V−1 the current consumption of NW-TFET LDO (1.5nA) is near two orders of magnitude lower than Line-TFET LDO (68nA) and three orders of magnitude lower than MOSFET LDO (9 µA). The Line-TFET LDO exhibits better results in almost all parameters despite of the gain-bandwidth product (GBW) that is in the same order of magnitude of the MOSFET LDO, 171 kHz compared to 250 kHz for gm/ID = 10.5 V−1. The comparison between TFET LDOs for gm/ID = 7 V−1 was also performed regarding the transient and process variability analysis. The transient response revealed that the Line-TFET LDO has a pronounced lower settling time, 71 µs compared to 5 ms for a load step, but with a damped oscillatory response, the NW-TFET LDO presented lower undershoot for the load step. The process variability analysis was performed for devices within the wafer and was observed that the Line-TFET LDO suffers a higher impact with a 20 dB variation on the loop gain in comparison to 10 dB in the NW-TFET LDO.

DRDebug: Automated Design Rule Debugging

Design rule checking (DRC) is an important step in the physical design flow that checks if a design meets the manufacturing constraints or design rules imposed by the process technology. It allows the foundry to ensure high acceptable manufacturing yield. Design rule verification is one of the most challenging steps because of the sheer size of the rule decks and the lack of standardization among these design rule manuals (DRMs). One way of efficiently discovering missed rule checks is by comparing the rule deck with that of another mature or well-established process. In this work, we develop two complementary techniques for comparing process design rule decks and automatically establishing a one-to-one correspondence between rules from two different process design kits (PDKs). The first approach, random layout generation (RLG), creates random layouts of different shapes and sizes. The generated layout is checked using both rule decks. The rules are then matched based on the violations generated. The second approach, based on rule language processing (RLP), matches rules based on the similarity between rule commands. Rules are directly matched based on the layer names and keywords present in the DRC commands. The two approaches are complementary and together they can correctly match more than 80% of the rules in two DRMs.