Abstract
We propose a rigorous SPICE simulation framework, compatible with industrial process design kits, to observe transient bit flips in CMOS SRAM due to the intrinsic transistor noise. The parameters of transient noise simulation are selected according to the noise behaviour and bandwidth of the inverter, however under CPU-time constraint. The methodology is illustrated in 28nm FD-SOI technology. We study the combined effects of the random telegraph noise, flicker and thermal noise sources, for the first time to our knowledge. The extracted mean times to failure (MTTF) are compared to those reported in the literature in extreme voltage, temperature and variability conditions. The MTTF spans from below 0.1ms to 108s, following a theoretical trend logMTTF∝VDD2.
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