A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance

Abstract

Synchronizers play a key role in multiclock domains systems on chip and their performance is usually measured by the mean-time between failures (MTBF) of the system. Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling for library flip-flop circuits in 65 nm and below. This degradation of parameters becomes critical when the system is operated under extreme supply voltage and temperature conditions. In this paper, we study the behavior of synchronizers in a broad range of supply voltage and temperature conditions. A new model for the metastability time constant ( $\tau $ ), the metastability window ( $T_{W}$ ), and MTBF is presented. We show a detailed comparison of model, measurements, and simulations for different technology nodes and discuss implications for modern synchronization systems. We propose design guidelines that account for supply voltage and temperature variations and determine the correct number of synchronizer stages required for target MTBF.