Priority Encoder Research Articles

Design of an Efficient Parallel Comparator Architecture for Low Power Delay Product

A binary comparator architecture is proposed in this work for static logic to achieve both low-power and high-performance operations. It also presents a detailed timing performance and power analysis of various state-of-the-art comparator designs. The main advantages of this design are its high speed and power efficiency maintained over a wide range of operands size, which is useful at low-input data activity environments. The proposed circuit design uses minimum fan-in and fan-out logic gates for achieving high speed and low power dissipation. Utilizing a 2-bit binary comparator circuit with minimum fan-in and fan-out of logic gates (NAND-NOR), the architecture of a parallel binary comparator is proposed for higher input operands by using a low radix multiplexer and priority encoder. Further, to decrease the size of the multiplexer and priority encoder by two times, a general architecture is also proposed by using a 4-bit binary comparator to reduce its complexity. The proposed circuits are optimized in terms of the power consumption and delay, which are due to low load capacitance, low leakages, and reduced dynamic power dissipation. Each of the proposed circuits has its own merits in terms of speed, power consumption, Power-Delay Product (PDP). Its synthesis is done on 180 nm as well as 90 nm CMOS technology using the Cadence tool. The physical layout of the proposed architecture using a 90 nm CMOS process (GPDK process) is also obtained.

Designing and Implementing a Fault-Tolerant Priority Encoder in QCA Nanotechnology

The quantum-dot cellular automata (QCA) is a new and impressive nano-technology for implementing electronic circuits at nanoscale. This nanotechnology is more impressive than CMOS technology in terms of higher speed, smaller area and less energy consumption, and can make significant progress in the design of logic circuits. quantum-dot cellular automata circuits are likely to have various defects during fabrication. In fabrication process, some different defects might be occurred (like cell deletion, cell addition, cell displacement, cell rotation, and misalignment). That’s why researchers are eager to design fault-tolerant circuits. In this paper, a fault-tolerant priority encoder is designed. For this purpose, a new fault tolerant majority gate is provided first. The results of simulations are shown with the QCADesigner software V2.0.3. The simulation results indicate an improvement in the performance of the proposed structure.

Design and implementation of asynchronous NOC architecture with buffer-less router

In present days, development in chip technology enables us to incorporate heterogonous cores on one chip. Synchronization and communication between such diverse cores is a major issue. Current Synchronous NOC architecture with buffered router consumes a substantial chip area and Power (clock distribution & I/O buffers). Hence in recent times Buffer-less routers based on Deflective routing are projected as a possible solution, but they suffers from issues like sequential port allocation and slow critical path and also increases the Latency. In this paper we propose 2D 4x4 Asynchronous Mesh NOC architecture with a novel router design using XY routing algorithm. In the proposed router design, we have eliminated the conventional input and output buffers and crossbar switch. We integrated priority encoder and FSM based Arbiter which efficiently solves long critical path issues of conventional Buffer less router by dynamically changing the port priority and hence solves the starvation and Live/Dead lock issue and improves the Area Consumption (i.e., reduced by ≈ 43%). We have used parallel transmission which enables us to improve Speed (by ≈73%) and elimination of I/O buffers reduces the power consumption (≈ 0.56w).

A Robust Encrypted Nanocommunication in QCA Circuit

Quantum-dot cellular automata (QCA) is an alternative technology developed to address the fundamental limitations of CMOS technology. This technology is attractive owing to its low power consumption, fast speed, and small dimensions. Cryptography can be a promising application of QCA technology. This paper describes a new way to generate encrypted patterns in QCA that can be helpful in QCA-based secure nano communication. We employed the round robin algorithm for encrypting data in nano communication. The proposed method is useful because it can be employed for the transmission of cipher text obtained using QCA without any limitation on the length of bits in a message. This method can also be used for creating encrypted patterns with high flexibility and scalability.Moreover, in this paper, a novel approximate eight-input majority gate is proposed, making it the first majority gate with even entries. This gate is suitable for designing digital logic circuits, such as priority encoders. However, this design is implemented in a single layer with only 13 cells. The proposed architecture of the majority gate was evaluated and simulated using the QCADesigner tool (version 2.0.3). The results showed 93% accuracy with eight inputs, which result in 256 states. Furthermore, one of these encrypted patterns was used for secure transmission the results approximate eight-input majority gate while considering error states that were recognized in the simulation as encryption keys; thus, we conducted error corrections accordingly.

Quantum dot celluar automata‐based encoder and priority encoder circuits: Low latency and area efficient design

AbstractThe transistorless technology, quantum dot cellular automata (QCA) becomes one of the potential candidates of nanotechnology for signal processing circuits because of its ultra‐low power requirement, high frequency of operation, extreme‐low area requirement, and short channel effect (SCEs) immune at nanoscale circuits. Quasi‐adiabatic switching of QCA makes its data transfer faster. This work reports faster, smaller, and low‐power, 4‐to‐2 and 8‐to‐3 encoder, and priority encoder circuits designed on QCA platform. Both of these encoders and priority encoders are widely used circuits for communication to encode the data. These circuits are realized using three‐input majority gates, five‐input majority gates, and co‐planar clock zone‐based crossover technique. The proposed circuits show the improvement in performance in terms of cell count, area requirement, delay, quantum cost, and energy dissipation as compared to the existing circuits. The cell count and the area requirement of the proposed circuits have been magnificently lowered as compared to the recent literature. Moreover, these circuits also require 75% lesser clock periods than the existing literature, thus demonstrate lower latency. This work shows the way for future exploration of QCA‐based encoder circuits.

Reversible priority encoder design and implementation using quantum‐dot cellular automata

Quantum-dot cellular automata (QCA) are the potential alternative to complementary metal–oxide–semiconductor-based technology. Ideally, zero power dissipation can be achieved with the help of reversible computing. In this study, a novel design of a reversible priority encoder based on QCA is proposed. The basic building blocks for the design are Toffoli and BJN gates. The proposed design is verified by the QCA designer simulator. The performance analysis of the reversible priority encoder is performed based on the simulation results. The proposedencoder not only overcomes the problem of the messy code but also declines the amount of heat energy dissipation through reversible logic. The proposed reversible circuit could be a major component in future wireless communication because reversible logic accounts for zero loss of information. The estimation of power consumption by proposed QCA circuits is explored that implies QCA can be an ideal platform to implement reversible circuits. The relationship with recently proposed work is also discussed.

Design of a Low Latency and High Throughput Packet Classification Module on FPGA Platform

The Packet classification method plays a significant role in most of the Network systems. These systems categories the incoming packets in various flows and takes suitable action based on the requirements. If the size of the network is vast and complexity will arise to perform the different operations, which affects the network performance and other constraints also. So there is the demand for high-speed packet classifiers to reduce the network complexity and improve the network performance. In this article, The Bit vector Packet classifier (BV-PC) Module is designed to improve the network system performance and overcome the existing limitation of Packet classification approaches on FPGA. The BV-PC Module contains Packet generation Unit (PGU) to receive the valid incoming packets, Memory Unit (MU) to store valid packets, Header Extractor Unit (HEU) extracts the IP Header address information from the Valid packets, The BV-Based Source and Destination Address (BV-SA, BV-DA) unit receives the IP packet header Information and Process with BV based rule set and aggregates the BV-SA and BV-DA outputs, Priority Encoder encodes the Highest priority BV Rule for the generation of Classified output. The BV-PC utilizes <2% Chip area (slices), works at 509.38MHz, and consumed Less 0.103 W of total Power on Artix-7 FPGA. The BV-PC operates with a latency of 5 clock cycles and works at 815.03Mpps throughput. The BV-PC is compared with existing approaches and provides Better improvements in Hardware constraints.

Design of low power fault tolerant flash ADC for instrumentation applications

Technological growth has remarkably put their efforts in making the electronic world a powerful one. Analog to digital converter (ADC) is said to be ancestor in the field of transforming analog information into digital form. It is a necessary component in RF and Mixed signal designs. This paper suggests both neither compact NOR based CMOS Linear Tuneable Transconductance Element (NOR-LTE) Comparator and Dynamic Priority Encoder (DPE). The NOR-LTE comparator reduces the power utilization and offset error, which improves the Power Supply Rejection Ratio (PSRR) of an overall circuit design. Dynamic Priority Encoder curtails the transistor count prescribed for Flash ADC. The proposed Fault Tolerant Flash ADC (FT-FADC) framework is implemented using Tanner EDA with 0.25 ​ ​μm CMOS technology. The above suggested FT- FADC achieves 3.44-bit ENOB at 1.5 ​V supply for 500 ​MHz Resolution Bandwidth (RSB). Due to high sampling rate 1.3 ​GS/s it upgrades the throughput rate by 60% and reduces the utilization of power by 47%.

A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree

In this article, a low-power, high-speed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a position-dependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zero-suppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allow interleaved latching of data at the output serializer. The design was implemented in a 65-nm LP-CMOS process for the readout of a $64\times64$ pixel array. Measurement results demonstrate a deadtimeless, full frame imaging rate of ~50 kfps, achieved with a dedicated output for every ( $32\times32$ ) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ.

Low power high performance priority encoder using 2D-array to 3D-array conversion

Abstract This paper discusses priority encoder and its designing complexity for higher number of input bits, i.e., 64, 128, 256, and so on. In order to reduce the complexity and power consumption of the circuit, a new circuit with three-directional (3D) array priority encoder is introduced. This 3D-array priority encoder circuit reduces the power consumption by 23.908 % and the transistors count by 19.572 % using 180nm technology, by using 45nm technology power consumption is reduced by 23.588% and transistors count remains same when compared to the existing two-directional (2D) array priority encoder. In this paper 64-bit input priority encoder is implemented using Cadence Virtuoso GPDK-180 nm and 45nm technology.

Diminution of power in load/store queue for CAM and SRAM-based out-of-order processors

In a modern world for non numeric applications, out-of-order super scalar processors are designed to achieve higher performance. Unfortunately the improvement in the performance has lead to the increase in the chip power and energy dissipation. The load/store queue is a one of the major power consuming unit in the data path design during dynamic scheduling. Load/store queue is designed to absorb busts in cache access and maintain the order of memory operations by keeping all in-flight memory instruction in program order. The proposed technique aims at reducing both dynamic and static power dissipation in the load/store queue (LQ/SQ) by using power-gating technique and priority encoder. Through this implementation, the least amount of redesign, verification efforts, lowest possible design risk, least hardware overhead is achieved without significant impact on the performance.

A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS

Although priority encoder (PE) plays a vital role in many applications, they perform poorly with large-sized input data. Our previous work tackles this problem by introducing a so-called one-dimensional-array to two-dimensional-array (1D-to-2D) conversion method, which can effectively handle up to a 4,096-bit PE. Taking advantage of the previous achievement, this paper further explores the benefit of a 1D-to-2D-based multi-match priority encoder (MPE). Specifically, compared with other designs implemented in ASIC and FPGA, the proposed PE and MPE outperformed by 4.4 times and 1.7 times, respectively. A 256-bit MPE chip fabricated in a 65-nm silicon-on-thin-buried-oxide (SOTB) CMOS process was also reported. The measurements showed that at 0.9-V supply voltage, the chip was fully operational at 50 MHz and consumed approximately 140.3 µW. More significantly, by exploiting the clock-gating and reverse back-gate biasing techniques, the standby leakage current at 0.6 V dropped to 1.12 nA, which is equivalent to the 0.67-nW standby leakage power.

Diminution of power in load/store queue for CAM and SRAM-based out-of-order processors

In a modern world for non numeric applications, out-of-order super scalar processors are designed to achieve higher performance. Unfortunately the improvement in the performance has lead to the increase in the chip power and energy dissipation. The load/store queue is a one of the major power consuming unit in the data path design during dynamic scheduling. Load/store queue is designed to absorb busts in cache access and maintain the order of memory operations by keeping all in-flight memory instruction in program order. The proposed technique aims at reducing both dynamic and static power dissipation in the load/store queue (LQ/SQ) by using power-gating technique and priority encoder. Through this implementation, the least amount of redesign, verification efforts, lowest possible design risk, least hardware overhead is achieved without significant impact on the performance.

Design of Low Power and High Speed Decoder and Priority Encoder using Carbon Nanotube Field Effect Transistor for Binary Content Addressable Memory Array

In this paper, design of Positive Feedback Adiabatic Logic (PFAL) based decoder and priority encoder using Carbon Nanotube Field Effect Transistor (CNTFET) for Binary Content Addressable Memory (BCAM) array is presented. The optimum set of CNTFET parameters such as number of tubes, chirality vector, pitch, dielectric constant and dielectric materials for low power and high speed encoder and decoder is used. The performance of proposed decoder and priority encoder is analyzed for average power, peak power and delay. Simulation results show that the proposed circuits outperforms compared to that of CMOS technology based circuits. The average power and peak power of the proposed decoder and priority encoder are in the range of μW while the range of values for CMOS based decoder are mW. The average delay of the proposed decoder is improved by 35.96% compared to that of CMOS based decoder. The average delay of the proposed priority encoder is improved by 30.77% compared to that of CMOS based priority encoder. All simulations are conducted for both CMOS and CNTFET based decoder and Priority encoder in HSPICE at 32 nm technology.

Design of Magnetic Non-Volatile TCAM With Priority-Decision in Memory Technology for High Speed, Low Power, and High Reliability

Recently, various magnetic non-volatile ternary content-addressable memory (MNV-TCAM) cells that use magnetic tunnel junctions (MTJs) as storage units have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption for search operation. In addition, the restrictions on the ordering of the TCAM array required by the using of the priority encoder to resolve the multiple match problem due to the `X' results in large delay and high energy consumption for update operation. To address these issues, the novel MNV-TCAM cell is first proposed, aiming to achieve high-speed, low-power, and high-reliable search operation. In addition to the search data operation, it can realize a search length operation. By exploiting this search length operation, we then present circuit-level design of the MNV-TCAM with a priority-decision in memory technology, which can utilize the length information of matched words sorted in an arbitrary order to decide the highest-priority matched word by performing a three-phase search operation. It implies that the restrictions on the ordering can be eliminated, thus, improving the update speed and energy-efficiency. Finally, hybrid CMOS/MTJ simulations are performed to demonstrate its functionality and evaluate its performance in terms of search reliability, search speed, and search energy consumption.

Ternary Content Addressable Memory With Improvised Search Efficiency

Content Addressable memories are advanced memories which can perform memory search in a single clock cycle. This also leads to higher power consumption and hence CAM are prone to exhibit high power dissipation during match operations. To overcome this drawback, an advanced Ternary Content Addressable Memories (TCAMs) are developed which are used in high-speed search Engines. The TCAM Smart CORE™ IP is a ternary content-addressable memory that stores {data, mask, value} entries with arbitrary data, mask and value bit strings. The mask is used to mask certain bits in the key field as “don’t care”. The retrieval of ‘value’ is based on a ternary match of ‘key’ with {data, mask}. In this paper to explain the TCAM which chooses a word from the stored ternary data based on its contents and then this compares with the search key from the continuous stored TCAM term in parallel and results in address of the matched term within one cycle. The function circuit of a TCAM is to store value in the cell and the stored value is compared with the corresponding states: 0, 1, and don't-care state as x. TCAM architecture is built by TCAM array cells and priority encoder (PE). Finally, this produces the matching lower address of the corresponding search key. So when compared with the existing CAM the proposed technique achieved best in time consumption.

A Low Power Flash ADC using Single-Electron Transistor

This paper proposes an analog-digital converter (ADC) using Single-electron transistor (SET).Single Electron Transistor is Nanodevice having a small quantum dot or island instead of the channel that works on the principle of Coulomb blockadewhich allows one electron tunnelingat a time from source to drain terminal. SET operates at low voltage and consumes lesspower. The proposed Flash ADC consists of SET based priority encoder and comparator circuits. The proposed design offers large input/output voltage swing, ultra-low power, compact circuit block for ADC compared to SET/CMOS hybrid amplifier-based ADC. In this paper, we have designed a 4-bit and 8bitFlash ADC using SET operating at room temperature and the performance estimationwas performed by using the CADENCE VIRTUOSO simulator.

Novel design of reversible priority encoder in quantum dot cellular automata based on Toffoli gate and Feynman gate

In accordance with Moore’s law, the size of complementary metal oxide semiconductor (CMOS)-based devices keep shrinking to augment the density on the chip. This scaling influences the execution of CMOS device due to several constraints like energy dissipation and synchronization of different components of the device. In non-reversible logic gates, power loss is the major concerned. Interest in reversible logic-based circuit design is increased as it offers reduced heat dissipation. Quantum dot cellular automata (QCA) is the possible implementation platform for reversible circuits. An encoder is an important component of memory, for address decoding and encoding. In this article, reversible logic-based architecture of 4 to 2 and 8 to 3 priority encoder is proposed and implemented on QCA platform. To design the encoder circuit, a new QCA layout of Feynman gate and Toffoli gate has been employed. The proposed layout of Feynman gate and Toffoli gate outshines the existing state-of-the-art designs. Quantum cost and circuit cost estimation of those encoder circuits are also performed. QCADesigner tool has been used to validate the performance of the proposed QCA reversible encoders.

Modified X–Y routing for mesh topology based NoC router on field programmable gate array

Network on chip (NoC) has been proposed as an enormously scalable solution to address communication problems in system on chip (SoC). The interconnections among multiple cores/multiple Intellectual Property modules on a chip have a major impact on communication and performance of the chip design in terms of area, throughput, latency and power. Hence, an efficient design of the NoC interconnect is of paramount importance. In this study, a novel idea of the NoC router using a single-side buffer in the input block and a programmable priority encoder in the scheduler is discussed and a 4 × 4 mesh topology based router design is implemented on a field programmable gate array device using these blocks. This gives an area optimisation of the router due to the use of a small buffer. Furthermore, a modified X–Y routing algorithm is discussed and implemented for the 8 × 8 mesh topology-based router. The result shows that the modified X–Y routing algorithm requires only two hops to reach any source destination pair resulting in latency optimisation of the NoC router. Thus, the router design with a single buffer and a modified X–Y routing algorithm provides the best solution for area and latency optimisation.

Power Efficient and Reliable Nonvolatile TCAM With Hi-PFO and Semi-Complementary Driver

In this paper, we propose a high priority first out (HiPFO) architecture of ternary content addressable memory (TCAM) to extend functions, not only “data comparison” but also “priority encoding.” With that architecture, we can select the longest matching prefix efficiently in terms of area and power consumption. We also introduce a semi-complementary data line driver (SCD <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and self-tuning VON (STV). With those techniques, we can eliminate the dc current in the data line and guarantee sensing margins even under small R-ratio nonvolatile memory in a 3T-2R-based HiPFO cell. As in experimental results, the PRAM-based HiPFO structure reduces the existing power consumption of priority encoder, thereby reducing the total power consumption by 27%. Also, thanks to the SCD <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the power loss from the dc current is reduced by more than 26%. In addition, the STV is helpful to overcome match line sensing margin at low R-ratio, which resulted in 1.5 times or larger sensing margin window improvement in the voltage swing of 1.2 V and R-ratio of 3. All those techniques are built in nvTCAM with 64-bit $\times$ 32 rows array, and showed 46% improvement of total power consumption with simulation. And the nvTCAM fabricated at 180-nm CMOS technology demonstrates HiPFO operation.