Power Efficient and Reliable Nonvolatile TCAM With Hi-PFO and Semi-Complementary Driver

Abstract

In this paper, we propose a high priority first out (HiPFO) architecture of ternary content addressable memory (TCAM) to extend functions, not only “data comparison” but also “priority encoding.” With that architecture, we can select the longest matching prefix efficiently in terms of area and power consumption. We also introduce a semi-complementary data line driver (SCD <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and self-tuning VON (STV). With those techniques, we can eliminate the dc current in the data line and guarantee sensing margins even under small R-ratio nonvolatile memory in a 3T-2R-based HiPFO cell. As in experimental results, the PRAM-based HiPFO structure reduces the existing power consumption of priority encoder, thereby reducing the total power consumption by 27%. Also, thanks to the SCD <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the power loss from the dc current is reduced by more than 26%. In addition, the STV is helpful to overcome match line sensing margin at low R-ratio, which resulted in 1.5 times or larger sensing margin window improvement in the voltage swing of 1.2 V and R-ratio of 3. All those techniques are built in nvTCAM with 64-bit $\times$ 32 rows array, and showed 46% improvement of total power consumption with simulation. And the nvTCAM fabricated at 180-nm CMOS technology demonstrates HiPFO operation.