Diminution of power in load/store queue for CAM and SRAM-based out-of-order processors

Abstract

In a modern world for non numeric applications, out-of-order super scalar processors are designed to achieve higher performance. Unfortunately the improvement in the performance has lead to the increase in the chip power and energy dissipation. The load/store queue is a one of the major power consuming unit in the data path design during dynamic scheduling. Load/store queue is designed to absorb busts in cache access and maintain the order of memory operations by keeping all in-flight memory instruction in program order. The proposed technique aims at reducing both dynamic and static power dissipation in the load/store queue (LQ/SQ) by using power-gating technique and priority encoder. Through this implementation, the least amount of redesign, verification efforts, lowest possible design risk, least hardware overhead is achieved without significant impact on the performance.