Design and implementation of asynchronous NOC architecture with buffer-less router

Abstract

In present days, development in chip technology enables us to incorporate heterogonous cores on one chip. Synchronization and communication between such diverse cores is a major issue. Current Synchronous NOC architecture with buffered router consumes a substantial chip area and Power (clock distribution & I/O buffers). Hence in recent times Buffer-less routers based on Deflective routing are projected as a possible solution, but they suffers from issues like sequential port allocation and slow critical path and also increases the Latency. In this paper we propose 2D 4x4 Asynchronous Mesh NOC architecture with a novel router design using XY routing algorithm. In the proposed router design, we have eliminated the conventional input and output buffers and crossbar switch. We integrated priority encoder and FSM based Arbiter which efficiently solves long critical path issues of conventional Buffer less router by dynamically changing the port priority and hence solves the starvation and Live/Dead lock issue and improves the Area Consumption (i.e., reduced by ≈ 43%). We have used parallel transmission which enables us to improve Speed (by ≈73%) and elimination of I/O buffers reduces the power consumption (≈ 0.56w).