Power Transistor Structure Research Articles

An Output-Capacitorless LDO regulator with fast transient response and high PSRR

Abstract A fast transient response and high supply voltage rejection ratio (PSRR) output-capacitor-less low-dropout (OCL-LDO) regulator with a dual power transistor structure is proposed in this paper. The designed flip voltage follower (FVF) structure and the proposed back-gate control loop improve the transient performance of the system. The proposed PSRR enhancement circuit transmits the power supply voltage fluctuation 1:1 to the gate of the power transistor so that the influence of the power supply voltage fluctuation on the output voltage of the LDO is offset by the difference between the gate and source voltages of the power transistor. The simulated results have shown that the proposed OCL-LDO regulator achieves full range stability from 100 μA to 50 mA. The output voltage undershoot is reduced by more than 100 mV when the load current is stepped from 1 to 50 mA in 500 ns without the load capacitor. The PSRR enhancement circuit increases the PSRR of the LDO from 1 KHz to 10 MHz by more than 20 dB.

Evaluation of the Perspective Power Transistor Structures on Efficiency Performance of PFC Circuit

The aim of this work is to investigate the influence of circuit elements on the properties of the selected power factor correction (PFC) topology. Active or passive PFC serves to increase the power factor (PF) and reduce the total harmonic distortion (THD) of the mains current. As a result, the distribution network is lightened due to its interference caused by connected electronic devices. An important indicator of all electronic converters is efficiency. Therefore, the work deals with the analysis of possible efficiency improvements in conjunction with the use of technologically new active components. Detailed experimental analyses and optimization procedures are performed in terms of the influence of transistor structures (SiC and GaN) on the qualitative indicators of the proposed PFC converter for a wide operating spectrum. The synthesis of the obtained results is given, together with recommendations for optimal selection and optimal design of PFC main circuit elements with regard to achieving peak efficiency values.

Current Trends in the Development of Normally-OFF GaN-on-Si Power Transistors and Power Modules: A Review

Gallium nitride (GaN) power transistors have attracted significant interest in the power electronics industry over the past decade as the next-generation power semiconductor devices. GaN power transistors are suitable for high power and high frequency applications due to their higher electron mobility, temperature tolerance, electrical conductivity, critical breakdown electric field, and breakdown voltage compared to the conventional silicon-based transistors and other wide bandgap (WBG) power transistors. In particular, GaN-on-silicon (GaN-on-Si) technology has opened up the possibility of manufacturing high-performance, low-cost WBG power devices in silicon-compatible fabrication facilities. The first GaN power transistor structure to be developed was the normally-ON depletion mode (D-mode) device. It relies on the highly mobile two-dimension electron gas (2DEG) at the GaN/AlGaN epitaxial layers’ interface to provide very low on-resistance. The normally-OFF enhancement mode (E-mode) GaN power transistor soon became available by controlling the 2DEG using various gate structures. This paper provides a review of the developments of GaN power transistors followed by a survey on current state-of-the-art GaN power technologies and applications, including comparisons between GaN growth substrates and developments of enhancement mode (E-mode) device structures and their process techniques. Moreover, developments of power module designs are also addressed, including gate driver designs and their requirements, and packaging techniques for power transistors and power modules.

A novel laminated gate to improve the ON-state resistance of LDMOS transistors

A novel power transistor structure, namely the laminated gate laterally diffused metal---oxide---semiconductor (LG-LDMOS) structure, is proposed herein. The proposed structure has an extra lateral gate located in the middle of the channel region in addition to the fin-shaped gate. This technique provides additional inversion channels. In this way, the channel resistance is reduced and also the power losses decrease due to improved gate control on the channel. The ON-state resistance of the proposed structure is improved by 52 % compared with a LDMOS structure with fin-shaped gate (Fin-LDMOS).

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Performance Comparison and Design Issue on Different GaN Power Transistor Structures

ABSTRACTThree types of Ganium Nitride (GaN) transistors were studied in this work. The devices were fabricated and exhibited unique characteristics over on-state current and off-state blocking performances. We also compared the performance differences of devices fabricated by multiepitaxial GaN/AlGaN layers on different substrates (Sapphire and Si) and evaluated the correlations among starting substrate, device variation, and manufacturing uniformity. The first device is a normally-on device with Sapphire substrate which shows good drain saturation current (Idsat) and breakdown characteristics, but the gate leakage current is quite large. The second device is a normally-off GaN transistor named metal-insulate-semiconductor (MIS) heterojunction field-effect transistor (MIS-HFET) which exhibits good performance with threshold voltage (Vth) of 3V and breakdown voltage (Vbd) of over 1800V. However the third device is a normally-off GaN metal-oxide-semiconductor field-elect transistor (MOSFET) structure which is rather difficult to exhibit good blocking characteristic due to inadequate doping process control of the reduce-surface-field (RESURF) region.

Measurement of swtitching losses in power transistor structure

Testing device designed for experimental examination of processes in power electronics devices during various switching modes is described. Through the use of auxiliary circuits additional switching modes (ZVS, ZCS) are realized except hard switching, and turning-off with reduced current respectively. The device’s advantage is possibility of fine dead time setting, allowing us analyzing effects of this phenomenon on measurements of commutation losses. Ill. 12, bibl. 10 (in English; summaries in English, Russian and Lithuanian).

Investigation of radiation-induced defects in the electron irradiated power transistor structures

The formation and annealing of radiation-induced defects in n-collector of power silicon transistor structures irradiated with fast electrons (E=4MeV) have been studied. It is found that the main stage of recovery of the minority carrier lifetime in the transistor collector region upon isochronal annealing occurs at temperatures corresponding to the disappearance of the vacancy–oxygen complex.

Insulated Gate P-I-N Transistor-a new MOS controlled switching power device

In this paper, a new monolithic MOS controlled power transistor structure called the Insulated Gate P-I-N Transistor (IGPT) is described for the first time and its operation is verified by two-dimensional numerical simulation. IGPT achieves an on-state voltage drop similar to that of a PIN diode, yet also provides insulated gate turn-off capability up to several thousand amperes per centimeter square. The turn-off of the IGPT is achieved by the MOS depletion of a high level injection region, verified also for the first time. IGPT is therefore a very attractive device to be used in high power switching applications because it is superior to current generation power devices such as the Insulated Gate Bipolar Transistor (IGBT) and MOS Controlled Thyristor (MCT). >

The minority carrier injection controlled field-effect transistor (MICFET): a new MOS-gated power transistor structure

A description is given of a power device structure, the minority carrier injection controlled field-effect transistor (MICFET), in which a floating p region coupled to the drain via a MOSFET is used to inject minority carriers (holes) into the JFET and upper drift region of the DMOSFET to modulate the conductivity of the device during the on-state. The results of device modeling, two-dimensional numerical simulation, and measurements performed on 500-V devices indicate a 30% improvement in on-state current density over the DMOSFET with comparable turn-off times.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Numerical modeling of power mosfets

The voltage limitations of UMOS vs VDMOS field-effect power transistor structures have been compared using 2-dimensional, 2-carrier numerical simulation for these devices in which the channel doping varies from source to drain. The electric field distribution at the surface and in the bulk is compared for these two structures. Premature voltage breakdown is predicted for the UMOS device caused by impact ionization due to the high electric field near the Si/SiO 2 interface.

Factors limiting current gain in power transistors

The combined effect of sidewall injection, bandgap narrowing, and Shockley-Hall-Read and Auger recombination in determining emitter efficiency in n-p-n power transistor structures is demonstrated by utilizing a two-dimensional transistor model. The relative importance of each of these effects is calculated as a function of emitter junction depth, emitter surface doping, and injection level. It is shown that in a practical transistor design the reduction in emitter efficiency due to the increased injection of holes into the emitter, resulting from bandgap narrowing caused by heavy doping, is not dominated by the emitter sidewall. Auger recombination is seen to be especially important when bandgap narrowing is present. Enhanced Auger-type recombination is due both to increased minority carrier injection in the emitter as well as current crowding effects. The predictions of the model are compared with results of the measurement of current gain versus current level characteristics on existing devices.

A 15-W monolithic power operational amplifier

The design of a new general-purpose monolithic power amplifier functional block is described and the flexibility of the block in various applications is discussed. The effects of thermal coupling on the die between components in high-gain dc power amplifiers are examined and a technique is presented for the analytical evaluation of dc circuit performance in the presence of these thermal interactions. Experimental results from the 15-W amplifier are presented. A new integrated power transistor structure is described that includes emitter degeneration resistors as part of the emitter structure. Circuit performance is summarized.

Epitaxial π-ν n-p-n high-voltage power transistors

A new silicon power-transistor structure has been developed which expands the frontiers of power-switching performance and high-voltage power-handling capability. This new structure employs a unique π-ν (nearly intrinsic p- and n-type) epitaxial-layer construction which utilizes overlay emitter concepts to achieve improved volt-ampere densities and expanded second-breakdown performance. An n+-p-π-ν-n+transistor structure is constructed using alternately grown π and ν, epitaxial high-resistivity layers, p-type base and n+emitter diffusions are used in the conventional manner to assure punch-through protection. The depletion region for the n+-p-π-ν-n+transistor is in the π base and the ν collector, and the maximum electrical field ( E_{\max} ) is at the π-ν interface. The avalanche breakdown V B of the device can be controlled by the thickness ( X_{n}, X_{p} ) and the concentration ( N_{A}, N_{D} ) of the π-ν layers. Limiting the thickness of the ν collector region and adjusting the thickness of the π base layer provides a transistor with optimum volt-ampere capability. Various π-ν structures have been fabricated and are evaluated electrically for power switching and for linear applications.

Thermal instability in power transistor structures

A time-dependent formulation is obtained for the two-dimensional heat-flow problem applied to a model for an interdigited power transistor structure. The treatment predicts that lateral thermal instability can arise at high power densities from the interaction of a local temperature rise within the transistor volume with the temperature dependence of the emitter current. A solution is offered which permits calculation of the effect of transistor design on the tendency toward thermal instability. It is seen that the presence of series emitter and base resistance can significantly improve device stability, especially at high currents where the dynamic emitter resistance becomes small and these resistances tend to limit the emitter current. This partly explains the more stable transistor operation at a given power level observed at high current-low voltage compared to high voltage-low current. Lateral instability can cause an order of magnitude reduction in the power-handling ability of a transistor compared to the case where only steady-state heating and maximum junction operating temperature are considered. A many-fold improvement in power capability is calculated for a transistor with emitter heat-sinking rather than the more conventional collector heat-sinking.

Heat transfer in power transistors

The internal heat transfer problem for a typical power-transistor structure has been solved analytically. The relations among current distribution, heat generation and temperature distribution have been derived. Usage of the resulting equations is illustrated by application to the most elementary problem, namely, uniform heat generation under the emitter.