Power Semiconductor Research Articles

A comprehensive study of defects in gallium oxide by density functional theory

Ultrawide bandgap gallium oxide (Ga2O3) is a promising material for power semiconductor devices and deep ultraviolet (UV) solar-blind photodetectors. Understanding the properties of point defects in Ga2O3 is necessary to realize better-performing devices. A comprehensive study based on density functional theory (DFT), using the generalized gradient approximation (GGA): Perdew-Burke-Ernzerhof (PBE) exchange–correlation functional, of point defects in corundum (α), monoclinic (β), and orthorhombic (ε) phases of Ga2O3 is presented. The point defects include vacancies, interstitials, antisites, and extrinsic impurities in various phases of Ga2O3. Defect formation energies, charge transition energy levels, and defect concentrations variation with temperature are listed and presented under both gallium-rich (Ga-rich) and oxygen-rich (O-rich) growth conditions. The formation energy diagrams predict that the Ga2O3 phases favor the formation of Ga and O vacancies and the incorporation of extrinsic impurities. The calculations also show that the charge transition levels are deep inside the bandgap regardless of the Ga2O3 phase and growth environment. The impacts of temperature on the intrinsic point defects are analyzed by probing the vibrational modes of β-Ga2O3 thin films grown in a metal–organic chemical vapor deposition (MOCVD) system at 700 °C temperature and annealed at 1100 °C in an O-rich environment.

Component-Level Semiconductor Loss Balancing for IGBT Based High Power MMC Through Insertion Index Modification

Modular multilevel converter (MMC) is the state-of-the-art converter topology in HVdc transmission applications. The reliability and lifetime of MMCs are strongly dependent on the health of the internal power semiconductors. The operating loss of power semiconductors, which is one of the dominant factors affecting component aging, is not uniformly distributed between the top and bottom switches in the same submodule (SM) due to the dc bias in the arm current. Such loss imbalance leads to differences in lifetime of semiconductors and reduces the reliability of SM. Especially under inverter conditions, the bottom insulated gate bipolar transistor (IGBT) in SM is subjected to a severe thermal stress and has a relatively high failure rate for the thermal vulnerability of IGBT. To extend the lifetime and improve the reliability, this article proposes a component-level loss balancing method. It is achieved by insertion index modification based on a feed-forward gain controller. The proposed method can improve the loss distribution among the top and bottom semiconductors without side effects on ac and dc outputs. Its effectiveness and feasibility are validated through simulation and experimental results.

Reduced Multisource Switched-Capacitor Multilevel Inverter Topologies

Multisource switched-capacitor multilevel inverters are proper topologies when multiple dc sources are available as renewable energy sources. However, these multilevel inverters have the main drawbacks of requiring a large number of power semiconductors and capacitors and a low boost factor to achieve a large number of voltage levels, which complicate control, reduce performance, and raise the cost. This article presents two configurations for multisource switched-capacitor multilevel inverters. First, a basic multisource switched-capacitor topology is proposed with a small number of capacitors and semiconductors that produce a zero voltage level and a large number of positive voltage levels. The input dc sources are operated in an asymmetric trinary algorithm, while the capacitors are charged/discharged in a binary algorithm using parallel/series modes (without the need for any circuit balancing). Based on the proposed basic topology, two multilevel inverter topologies are proposed, which create bipolar output voltage levels using two different circuits at the output. The first proposed topology uses a standard H-bridge inverter at the output of the basic topology, while the second topology uses an extra switched-capacitor (self-balancing) circuit. The comparison indicates that both the proposed topologies have advantages over most of the reported multisource switched-capacitor multilevel inverters, such as a small number of capacitors, a small number of power semiconductors, low voltage stress, and high boost factor. Furthermore, the proposed topologies decrease the low cost factor in comparison to other topologies. The capacitors' capacitance, power losses, and voltage ripple losses are all measured and evaluated in detail. Theoretical research is validated with the use of laboratory prototypes to validate the performance of the proposed topologies.

New Dual-Source High-Gain ZVS DC-DC Converter for Integrating Renewable Power Source and Battery Storage

A new soft-switching high-gain two-source dc-dc boost converter is proposed here. The proposed converter provides two bidirectional and unidirectional input ports, handling the energies of a battery storage and a renewable power source, respectively, to supply a resistive load through a switched-capacitor (SC) voltage multiplier. As a result, three power switches, four power diodes, two inductors and four capacitors are used in the converter structure. The ZVS of all power switches is realized without any auxiliary circuit and in whole power ranges of the converter input sources and the output load. The converter power MOSFETs are switched in PWM manner with two individual duty ratios, allowing to regulate the output voltage and control the power coming from the input unidirectional port. Depending on the converter duty ratios, its basic operation principle is analyzed in two different operation cases. The behavior of the proposed converter is analytically investigated, and a low-power laboratory prototype is built to evaluate the converter performance in different operation conditions. The proposed converter benefits from simple and compact structure, minimum number of power switches and magnetic elements, reduced voltage stress across the power semiconductor devices, high voltage gain and high efficiency.

An On-Line Calibration Method for TSEP-Based Junction Temperature Estimation

Temperature sensitive electrical parameters (TSEP) provide an indirect and noninvasive method for on-line junction temperature estimation of power semiconductor devices. It is known that the fundamental of TSEP-based methods is to calibrate the relationship between TSEP and junction temperature in advance. However, the calibration methods in the literature need to open the module, require pretesting, or record the operating data of a converter in the entire power rating range, which are inconvenient in field applications. This article proposes an on-line and noninvasive calibration method by measuring the data at three operating states that are already existed in the regular converter operation. It is achieved by measuring the accessible heatsink/case temperature and TSEP during converter regular operation. The concept, implementation, and error analysis of the proposed method are presented in this article. Experimental verification is given to prove the effectiveness, accuracy, and convenience of the proposed method.

The Advantages and Applications of IGBT Compared with Conventional BJT and MOSFET

Nowadays, the power semiconductor devices have been used in many fields like wind power generation systems, the rail transit. Bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) as well as some other devices are the dominating the market. The insulated gate bipolar transistor (IGBT) as a mixed device of the BJT and the MOSFET, has a preeminent performance. In this paper, the characteristics of the punch through IGBT (PT-IGBT), the MOSFET and the BJT will be investigated by TCAD. Then the PT-IGBT is compared with the BJT and the MOSFET, for concluding its advantages. According to the simulation result, the PT-IGBT has the on-state current of 9*10-4A and the forward blocking voltage of 1200V, which are much higher than the other two devices. In the end of the paper, the development of the semiconductor devices is predicted, about the research trends.

Design and Optimization of Gate Driver Integrated Multichip 3-D GaN Power Module

Gallium nitride (GaN) high electron mobility transistors (HEMTs) are excellent power semiconductor devices due to their superior material properties compared to their silicon (Si) counterparts. It has demonstrated a fast switching speed with high dV/dt, enabling the designer to push the switching frequency toward the MHz range. However, traditional wire-bonded packaging becomes a limiting factor in fully harnessing the benefits offered by these advanced power devices, as it is likely to introduce voltage overshoot, oscillation, parasitic turn-on, and electromagnetic interference (EMI) issues; thus, improved and advanced packaging structures are a must to bridge the gap. Besides, the unique electrical behavior and footprint of GaN compared to Si and Si carbide make them have different requirements for power module integration. To seek a viable solution, a globally optimized double-sided cooled, gate driver integrated 650-V/60-A GaN half-bridge power module is presented herein. The proposed 3-D integrated hybrid solution delivers an optimized package, having power loop inductance and thermal resistance as low as 0.91 nH and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.38~^{\circ }\text{C}$ </tex-math></inline-formula> /W, respectively, which is verified using simulation and experimental results. The overall utility of the design improved proportionately by introducing simple, yet effective electrical/thermal codesign approaches, which can be applied to future power modules, designed for separate applications.

Active Thermal Control for Buck Converter-Based Active Power Decoupling Circuit

Aluminum electrolytic capacitors (AECs) and power semiconductor devices (PSDs) are typically identified as weak links in the reliable design of power converters. To eliminate the AECs from the design, active power decoupling (APD) circuits are preferred in single-phase power converters. However, in an attempt to eliminate AECs, this approach introduces the latter weak link in the design, i.e., PSDs in the APD circuit. This article proposes an active thermal control technique to improve the reliability of PSDs in the buck APD circuit. The proposed technique reduces the swing in junction temperature of PSDs using noninvasive power loss modulation. The power loss in PSDs is changed by varying the average voltage across the buffer capacitor. Further, a control technique is suggested to synthesize the reference for average voltage across buffer capacitor. This controller accounts for nonlinearities and minimum/maximum limits of power loss modulation. Further, the additional energy loss due to power loss modulation is restricted to a predefined limit. The proposed technique is validated with the help of circuit simulations and experimental studies with a 500 W laboratory prototype. For the selected mission profile, an increase of 28.5% in the lifetime of PSDs in buck APD circuit is estimated.

A Modular Bidirectional Solid-State DC Circuit Breaker for LV and MVDC Grid Applications

Direct current (dc) microgrids are increasingly gaining attention in industrial applications due to their simpler and more efficient integration with renewable energy resources and energy storage elements. The dc grid demands a faster, compact, cost-effective, and fault-tolerant protective system for reliable operation. To address the above challenges, this article proposes a bidirectional solid-state dc circuit breaker topology that guarantees reliable operation of dc grids [low voltage dc (LVDC) and medium voltage dc (MVDC)]. A modular extension of the proposed circuit breaker is also presented, resulting in better reliability, scalability, and fault-tolerant operation. The circuit breaker is derived using power semiconductor devices [silicon-controlled rectifiers (SCRs) and insulated-gate bipolar transistors (IGBTs)], with SCR acting as a main power interruption device. Salient features of the proposed topology include modularity, use of low-power rated devices, low-current rated sensors, and pre-fault interruption. A detailed mathematical analysis validating the design and operation of the proposed modular circuit breaker is presented. Moreover, the article also highlights the merits and limitations of the proposed concept. Finally, a laboratory prototype is developed with a system specification of 400 VDC/14 A to validate the performance of the proposed circuit breaker with single and modular operations, which is in line with the obtained simulation results. To verify current sharing between the modules, a few non-ideal conditions such as the use of non-identical main SCRs and turn-on delay are considered and tested on the developed prototype.

Hybrid-Mode Adaptive Zero-Voltage Switching for Single-Phase DC–AC Conversion With Paralleled SiC MOSFETs

State-of-the-art soft-switching modulations such as critical conduction mode and triangular current mode increase the conduction loss of power semiconductors and require variable switching frequencies; thus, these soft-switching methods are seldom used in high-power dc–ac conversion. To achieve soft-switching while maintaining low root mean square currents, this article proposes a hybrid quadrilateral and continuous current mode (HQCCM) modulation for general high-frequency single-phase dc–ac conversion based on paralleled silicon carbide metal oxide semiconductor field-effect transistors. The proposed HQCCM adaptively operates in soft-switching quadrilateral current mode or hard-switching continuous conduction mode in one ac line cycle depending on the instantaneous ac load current. Thus, high efficiencies can be achieved over the full power range. This HQCCM modulation features adaptive soft-switching, constant switching frequency, and compatibility to line filter and is applicable for high-power applications. A 4.4-kW single-phase dc–ac inverter is developed and tested to verify the advantages of the HQCCM. This article is accompanied by a video demonstrating the effectiveness of the proposed HQCCM in varying load scenarios.

An Online Condition Monitor Method for IGBT Independent of Collector Current

Junction temperature monitoring and fault diagnosis of power semiconductor devices can provide critical information to ensure the reliable operation of power electronic systems. In this article, an online condition monitoring method for insulated gate bipolar transistors (IGBTs), which is not affected by the collector current, is proposed based on the Miller voltage plateau of the conduction process. The relationship between the Miller voltage plateau and the junction temperature is analyzed, and an analytical model of the Miller voltage against junction temperature is established. By using this model and the conducting-state characteristics of the device, a reverse current phase measuring strategy is proposed to decouple the influence of the collector current on the junction temperature estimation, and an online measurement circuit of the Miller voltage is designed. In addition, the characteristics of the trigger voltage under different faults are analyzed to recognize fault types. The experimental results show that the proposed method has high sensitivity and good linearity. It is proven that the proposed measurement strategy is independent of the collector current, which can accurately distinguish the fault forms of IGBTs.

A Cost-Effective and DC-Fault Tolerant Alternate Arm Converter With Wide Range Voltage Adaptability

In this article, an enhanced three-arm alternate arm multilevel converter (AAMC), called T-type AAMC (T-AAMC), is proposed for achieving dc fault ride-through capability with reduced semiconductor power devices compared to the hybrid modular multilevel converter (MMC). The upper and lower dc arms of T-AAMC are formed by half-bridge submodules (SMs) and series devices for lower construction costs, while the ac arm uses full-bridge SMs to realize dc fault tolerance. First, the arm phase-shift conducting modulation is applied for energy balance of converter stacks under wide-range operation by adjusting the arm phase-shift angle to match ac grid voltage and power factor. Then, the SM number, power device number, and SM capacitance are evaluated for T-AAMC under optimized modulation design. Analyses illustrate that 43% SMs, 17% power devices, and 44% energy storage requirement are reduced with the proposed topology than that with hybrid MMC. Furthermore, the closed-loop control system is designed to dynamically regulate the energy sharing between dc and ac stacks. Finally, full-scale simulations and down-scaled experiments are performed to verify the feasibility of the proposed converter and the theoretical analysis of its modulation and implementation.

Analysis of an LLC–DAB integrated DC–DC converter topology with low loss and low cost

AbstractThis paper proposes an LLC‐DAB integrated high‐frequency isolated DC–DC converter topology structure to reduce the loss and cost of the DC power distribution system. Furthermore, the complexity and efficiency of the system also can be improved. The proposed converter consists of a DAB converter and two input‐parallel‐output‐parallel half‐bridge LLC resonant converters. It provides two DC voltage level buses, namely the HVDC bus and the LVDC bus. Compared with the typical converter topology of the DC power distribution system, the number of power semiconductors of the proposed converter topology is reduced by sharing the power semiconductors of the DAB converter and LLC resonant converter. As a result, with the number of power semiconductors decreasing, the cost and loss of the system are reduced. Moreover, the proposed converter can control the flow direction of power conversion and supply power to the loads. The single‐phase‐shift modulation method is adopted for the DAB converter, and two LLC resonant converters operate as the DC transformer under resonant frequency with open‐loop control. The operation principles and characteristics of the proposed converter are discussed. Finally, the simulation is carried out and an experimental prototype is developed to verify the effectiveness of the proposed topology.

Insulated Gate Bipolar Transistor Solder Layer Defect Detection Research Based on Improved YOLOv5

The expanding market scale of the insulated gate bipolar transistor as a new type of power semiconductor device has higher insulated gate bipolar transistor soldering requirements. However, there are some small bubbles difficult to detect. The accuracy and speed of existing detection algorithms are difficult to meet the requirements of automated quality monitoring. For solving these problems, a detection data set of solder layer images captured by X-ray and labeled was made and an improved algorithm based on YOLOv5 was proposed, which can detect defects accurately and at a fast speed. The main contributions of this research are as follows: (1) a tiny bubble detection layer that further integrates the deep feature information and shallow feature information is added to improve the model’s ability to detect small bubbles; (2) to speed up model convergence by optimizing anchor frame parameters; (3) we change the EIoU loss function as the bounding box loss function to solve the sample imbalance of the dataset; (4) combine the Swin Transformer structure to improve the convolution module and form a new feature extraction module, and introduce it into the backbone layer to improve the detection accuracy. The results of the experiment show that the overall performance of the improved network is better than the original and mainstream detection algorithms. The accuracy of the improved YOLOv5_SEST has reached 94.5% and 5.6% improvement in mAP for common bubble defect detection compared to the original algorithm. Our model size is only 5.3 MB, and the detection speed reaches 110 f/s. Therefore, the improved YOLOv5_SEST can well meet the requirements of automated quality monitoring of insulated gate bipolar transistors.

Performance investigation of modular multilevel inverter topologies for photovoltaic applications with minimal switches

Introduction. In recent years, a growing variety of technical applications have necessitated the employment of more powerful equipment. Power electronics and megawatt power levels are required in far too many medium voltage motor drives and utility applications. It is challenging to incorporate a medium voltage grid with only one power semiconductor that has been extensively modified. As a result, in high power and medium voltage settings, multiple power converter structure has been offered as a solution. A multilevel converter has high power ratings while also allowing for the utilization of renewable energy sources. Renewable energy sources such as photovoltaic, wind, and fuel cells may be readily connected to a multilevel inverter topology for enhanced outcomes. The novelty of the proposed work consists of a novel modular inverter structure for solar applications that uses fewer switches. Purpose. The proposed architecture is to decrease the number of switches and Total Harmonic Distortions. There is no need for passive filters, and the proposed design enhances power quality by creating distortion-free sinusoidal output voltage as the level count grows while also lowering power losses. Methods. The proposed topology is implemented with MATLAB / Simulink, using gating pulses and various pulse width modulation methodologies. Moreover, the proposed model also has been validated and compared to the hardware system. Results. Total harmonic distortion, number of power switches, output voltage and number of DC sources are compared with conventional topologies. Practical value. The proposed topology has been very supportive for implementing photovoltaic based multilevel inverter, which is connected to large demand in grid.

Improving the thermal properties of the device in the process of forming a contact with the collector region of a silicon transistor

Objective. The objective of the study is to increase the reliability of the contact of the semiconductor transistor crystal to the body and the reproducibility of the technological process.Method. A method for obtaining multilayer metallization of the reverse side of the crystal has been developed and the most optimal technological modes of its formation have been selected. The parameters of the reliability of the connection of the crystal to the body of the transistor were checked.Results. Layer-by-layer metallization has been obtained, which provides a strong contact to the collector region of the transistor and a reliable fit of the crystal to the base of the case.The control of technological operations showed 100% distribution of solder over the surface of the crystal, the absence of pores in the solder, the improvement in the output characteristics of the device and the increase in the percentage of output usable transistors.Conclusion. An analysis of the experimental results showed that in order to create a reliable contact and remove heat from the collector junction of power semiconductor transistors on the reverse side of the plates, it is necessary to form a metallization in one technological cycle, consisting of four layers of metals (Cr-Ni-Sn-Ag). The technical result of the research is to improve the quality of fit by obtaining a uniform distribution of the layer of Cr-Ni-Sn-Ag metals in a single technological cycle.

Innovative ceramic-matrix composite substrates with tunable electrical conductivity for high-power applications

ABSTRACT A wide band gap semiconductor power module can operate at higher voltages as compared with its traditional silicon counterpart. However, its insulating system undergoes stronger electric fields at the triple point between the ceramic substrate, the metallic tracks and the encapsulating polymer, which can dramatically reduce its lifespan. Here we report an original concept based on the local modification of the substrate properties to mitigate such electrical stress. Numerical simulations revealed its potential to reduce this constraint by up to 50%. This concept was realized by developing, through a practical approach, a novel substrate made of an AlN-based ceramic (material A) integrating a nanocomposite volume endowed with controlled properties and geometry. This approach implies first the spark plasma sintering of the AlN powder with additives (Y2O3, CaF2) to endow the material A with a very low electrical conductivity (σ) and high thermal conductivity (k). Graphene nanoplatelets (GNP) were incorporated within this material to fabricate a nanocomposite with a controlled σ anisotropy that otherwise reached a striking ratio of 106 at 20°C for 1.25 vol% GNP. Our approach secondly aimed at developing an effective process allowing to integrate this nanocomposite into the material A with a very high degree of reproducibility. It finally consisted in establishing the electrical contacts on the achieved substrate and encapsulating it for breakdown testing. The novel substrate enabled a mitigation of the electrical constraint by diminishing its intensity and shifting it from the triple point to a less constrained area. It already brought an improvement in breakdown voltage (VB) by 15% as compared to the traditional substrate, and revealed the potential for achieving higher VB as well. This work lays the foundation for the development of novel multifunctional ceramic-matrix composite substrates sought for power electronics as well as for other potential applications.

Suppression of stacking-fault expansion in 4H-SiC PiN diodes using proton implantation to solve bipolar degradation

4H-SiC has been commercialized as a material for power semiconductor devices. However, the long-term reliability of 4H-SiC devices is a barrier to their widespread application, and the most important reliability issue in 4H-SiC devices is bipolar degradation. This degradation is caused by the expansion of single Shockley stacking-faults (1SSFs) from basal plane dislocations in the 4H-SiC crystal. Here, we present a method for suppressing the 1SSF expansion by proton implantation on a 4H-SiC epitaxial wafer. PiN diodes fabricated on a proton-implanted wafer show current–voltage characteristics similar to those of PiN diodes without proton implantation. In contrast, the expansion of 1SSFs is effectively suppressed in PiN diodes with proton implantation. Therefore, proton implantation into 4H-SiC epitaxial wafers is an effective method for suppressing bipolar degradation in 4H-SiC power-semiconductor devices while maintaining device performance. This result contributes to the development of highly reliable 4H-SiC devices.

Visible laser attenuation characteristics using various polymeric nanocomposites

The attenuation characteristic of a semiconductor laser and green laser beam power with various polymer nanocomposites including PbS, TiO2, V2O5, and CuO are investigated experimentally. Various polymeric nanocomposites with the same concentration of different nanoparticles were prepared using a solution casting technique. The distance between the sample and detector as well as the sample and laser source, and the laser beam incident angle on the surface of the sample are found to be important factors to obtain robust measurements of the attenuation of the semiconductor and green laser beam power. The nanocomposite thin film doped with CuO has more laser beam power attenuation compared to the other prepared nanocomposite thin films. Polymer nanocomposites have various applications, e.g., cut-off laser filters, optical limiting laser, and laser beam power attenuation.

Digital Control and Power Systems for the Pegasus-III Experiment

The PEGASUS-III experiment is a solenoid-free, low aspect ratio spherical tokamak that will serve as a dedicated U.S. platform for comparative nonsolenoidal tokamak plasma startup studies. Approximately 175 megavolt-ampere (MVA) of reconfigured and expanded programmable power systems, 7 MJ of new stored energy, and new digital control and protection systems for the facility are being commissioned to support PEGASUS-III upgrades. These include: increased toroidal field (0.15–0.6 T); new divertor and poloidal field coils; increased pulse length; local and coaxial helicity injectors for solenoid-free plasma initiation; radio frequency (RF) systems for heating and current drive; and a diagnostic neutral beam (DNB). A new real-time digital control system implements 16 proportional-integral differential (PID) feedback controllers with 25 kHz loop rates to control the electromagnets and helicity injectors. The poloidal field coils, helicity injector arc currents, and toroidal field are driven by 36 3.6 MVA (4 kA, 900 V) insulated-gate bipolar transistor (IGBT) buck converters. Helicity injector bias voltage and current will be provided by a set of four 10.8 MVA multi-level buck converters (MLBCs). Each is comprised of an 1800 V integrated gate-commutated thyristor (IGCT) stage and a ±900 V IGBT stage in series, providing controllable <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {inj}}\le 4$ </tex-math></inline-formula> kA at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {inj}}\le 2.7$ </tex-math></inline-formula> kV. A field programmable gate array (FPGA)-based digital fault protection system multiplexes controller commands to individual power semiconductors in these supplies, monitors their operational status, and executes shutdown sequences within <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10~\mu \text{s}$ </tex-math></inline-formula> of fault detection. An 80 kV, 4 A zero-voltage-switching (ZVS) resonant converter with < 1% output ripple is under development for the DNB and is being evaluated as a topology to drive RF sources.