Power Semiconductor Packaging Research Articles

Highly Robust, Pressureless Silver Sinter-Bonding Technology Using PMMA Combustion for Power Semiconductor Applications

This study presents the development of a highly robust, pressureless, and void-free silver sinter-bonding technology for power semiconductor packaging. A bimodal silver paste containing silver nanoparticles and sub-micron particles was used, with polymethyl methacrylate (PMMA) as an additive to provide additional thermal energy during sintering. This enabled rapid sintering and the formation of a dense, void-free bonding joint. The effects of sintering temperature and PMMA content on shear strength and microstructure were systematically investigated. The results showed that the shear strength increased with rising sintering temperatures, achieving a maximum of 41 MPa at 300 °C, with minimal void formation due to enhanced particle necking facilitated by PMMA combustion. However, at 350 °C, the shear strength decreased to 35 MPa due to cracks and voids at the copper substrate–copper oxide interface caused by thermal expansion mismatch. The optimal PMMA content was found to be 5 wt.%, balancing sufficient thermal energy and void reduction. This pressureless sintering technology demonstrates significant potential for high-reliability applications in power semiconductor modules operating under high-temperature and high-stress conditions.

Enhanced thermal conductivity of epoxy resin by incorporating three-dimensional boron nitride thermally conductive network.

Packaging insulation materials with high thermal conductivity and excellent dielectric properties are favorable to meet the high demand and rapid development of third generation power semiconductors. In this study, we propose to improve the thermal conductivity of epoxy resin (EP) by incorporating a three-dimensional boron nitride thermally conductive network. Detailedly, polyurethane foam (PU) was used as a supporter, and boron nitride nanosheets (BNNSs) were loaded onto the PU supporter through chemical bonding (BNNS@PU). After immersing BNNS@PU into the EP resin, EP-based thermally conductive composites were prepared by vacuum-assisted impregnation. Fourier transform infrared spectrometer and scanning electron microscope were used to characterize the chemical bonding and morphological structure of BNNS@PU, respectively. The content of BNNS in BNNS@PU/EP composites was quantitatively analyzed by TGA. The results show that the thermal conductivity of the BNNS@PU/EP composites reaches 0.521 W/m K with an enhancement rate η of 30.89 at an ultra-low BNNS filler content (5.93 wt. %). Additionally, the BNNS@PU/EP composites have excellent dielectric properties with the frequency range from 101 to 106Hz. This paper provides an interesting idea for developing high thermal conductivity insulating materials used for power semiconductor packaging.

Interface regulation of micro-sized sintered Ag-10Al composite based on in-situ surface modification and enhanced microstructure stability in power electronic packaging

The increasing demand for high-power SiC semiconductors necessitate the development of a die attachment material that combines high-temperature resistance, reliability, and cost-effectiveness. In this study, a novel micro-sized composite, Ag-10Al paste, containing 10 wt% Al particles, was designed. A remarkable phenomenon, the ejection of ultrafine Ag nanoparticles from micron-sized Ag flakes, was observed for the first time. The phenomenon was utilized for the in-situ surface modification of Al. Subsequently, the microstructure and mechanical properties of the sintered Ag-10Al/direct bonded copper (DBC) joints were studied. Results indicated that the Ag-10Al composite exhibited superior microstructure stability compared to sintered Ag. The Ag/Al interface was systematically analyzed, revealing a unique Ag/nano Ag2O/Al2O3 amorphous/Al structure. This structure was formed through the Ag nanoparticle jetting effect of Ag flakes, achieving effective bonding between nano Ag2O and Al2O3 amorphous phases through mutual dissolution at the atomic level. Moreover, the sintered Ag-10Al joint demonstrated enhanced mechanical performance stability over the sintered Ag joint. After 1000 h aging at 300 ℃, the shear strength of the sintered Ag-10Al joint reached 34.1 MPa, meeting the requirements for power semiconductor packaging. In conclusion, the Ag-10Al composite paste was thoughtfully designed, excelling in both performance and cost-effectiveness.

A Computational Multiscale Modeling Method for Nanosilver-Sintered Joints with Stochastically Distributed Voids

A high power density is required in wide band gap power semiconductor packaging, which has led to the popularity of sintered nanosilver as an interconnecting material. However, affected by stochastically distributed voids in its microstructure, this material in practice exhibits instability leading to reduced reliability. In this paper, a computational multiscale modeling method is proposed to simulate the influence of micro-voids on macro-properties, providing an efficient tool to analyze the aforementioned problem. At the micro-scale, the three-parameter Weibull distribution of the equivalent Young’s modulus and the normal distribution of the equivalent Poisson’s ratio are captured by Monte Carlo-based finite element simulation on the reconstructed stochastic representative elements, where the density and distribution morphology of micro-voids are taken into consideration. At the macro-scale, the effect of the microscopic voids is transferred through a random sampling process to construct the multiscale model. The effectiveness and validity of the proposed method are verified through experimental case studies involving the modeling of nanosilver-sintered joints sintered at temperatures of 275°C and 300°C. In addition, the effects of the sintering temperature on the dispersion of the micro-voids, the distribution fluctuation of the constitutive parameters, and the mechanical properties are also discussed based on numerical and experimental results.Graphical

SiC Die Attach Based on Sintered for Wide Band Gap Semiconductor

Silver sintered die attach materials offer a new interconnect technology. Hybrid sintering die attach paste is resin-based and has the same application as standard die attach paste applications, but it does not require high pressure and high temperature for sintering. It features excellent workability that enables stable application for 24 continuous hours, without silver sedimentation or separation. Lead-free die attach materials that offer simplified processing, robust reliability and best-in-class thermal and electrical performance for high power semiconductor packages. SiC is next generation Wide Band Gap semiconductor material for high temperature power electronics for automotive and telecommunication. We would like to introduce a SiC die attach based on sintering solution for WBG packages. Features is thermal conductivity >200 W/m.k, pressure less die attach process, low temperature cure under nitrogen atmosphere, and any treated surface excellent adhesion to all treated surfaces.

Objective-Based Low-Frequency Parasitic Inductance Characterization Method for Power Semiconductor Package With High Power and Switching Speed

Characterizing package parasitic inductance is significant for package design, dynamic characteristic evaluation, thermal management, and insulation breakdown protection. As package parasitic inductances become smaller and the switching speed of the power semiconductor becomes higher, traditional and widely-used double pulse tests based on the “ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> = <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> /( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di</i> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i> )” and “ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> = 1/(4π <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> )” present more critical drawbacks in accuracy and adaptability. This paper proposes a novel method called objective-based low-frequency-range parasitic inductance characterization to accurately obtain the parasitic inductance of semiconductor packages. The proposed method directly extracts the package inductances instead of the current commutation loop and can be carried out under low bus voltage and low frequency. Thus, the proposed method features higher robustness, adaptability, and accuracy. Experimental results in the commercial SiC power device/module validate the feasibility and superiority of the proposed method.

Review of Topside Interconnections for Wide Bandgap Power Semiconductor Packaging

Due to their superior material properties, wide bandgap (WBG) semiconductors enable the application of power electronics at higher temperature operation, higher frequencies, and higher efficiencies compared to silicon (Si). However, the commonly-used aluminum wire bonding as topside interconnection technology prevents WBG semiconductors from reaching their full potential, due to inherent parasitic inductances, large size, heat dissipation, and reliability issues of wire bonding technology. Therefore, this article presents a comprehensive review of topside interconnection technologies of WBG semiconductor power devices and modules. First, the challenges and driving factors for the interconnection of WBG semiconductor dies are discussed. Second, for each widely commercially used WBG semiconductor, i.e., silicon carbide and gallium nitride, technical details and innovative features of state-of-the-art interconnection techniques in packages are reviewed. Then, the majority of existing topside interconnection materials for WBG semiconductors are categorized and compared, followed by a discussion of their advantages, challenges, and failure modes. Based on this elaborate discussion, potential future directions of the interconnection technology development are given. It is concluded that the superior performance of WBG semiconductors can be obtained by combining novel materials with innovative designs for the topside interconnections.

Copper to resin adhesion characterization for power electronics application: Fracture toughness and cohesive zone analysis

The use of molding compound as encapsulant is nowadays increasing in semiconductor power module applications. The adhesion of package interfaces between copper components and molding compound is one of the key aspect for an improved durability. The presented activity proposes the fracture toughness characterization of copper–resin interface in a power semiconductor package due to different experimental tests and the cohesive zone method to describe interfacial fracture. Double Cantilever Beam (DCB) and Four Point Bending (FPB) tests have been executed on dedicated bi-material coupons. The scope of these trials has been to enhance two different propagation modes based on different ratio between mode-I (opening) and mode-II (sliding) according to a mixed-mode approach. Strain energy release rate (SERR) and mode-mixity have been estimated by a finite element analysis based on the virtual crack closure technique (VCCT) and the crack surface displacement method (CSD). The information about fracture toughness at two different mode mixity have been considered to predict the SERR for every arbitrary mode mixity. Finally, dedicated finite element models based on cohesive elements have been developed and calibrated considering the fracture toughness experimental values and the measured force–displacements behavior during the two considered tests. Dedicated physical analyses have been carried out to validate the proposed method.

GE SiC Semiconductor Device Operation at Extreme Temperatures

Abstract GE Research has been working on the design, packaging, and testing of SiC Power semiconductors devices at junction temperatures up to 500°C for the past 5 years. Intrinsically, SiC power devices are able to endure and operate reliably at harsh environments. Limiting factors to packaged devices’ operation at high temperature are the contact metallization and packaging. While testing bare die power devices, probe contact resistance was found to be an issue for resistance measurements at very high temperatures. On the backside contact, traditional die attach solders have operational temperature limits. Using insulated metal substrates, sintered die attach, and wedge bond interconnect, GE Research tested its power devices up to 500°C junction temperature. GE Research also demonstrated various junction termination dielectric stackups which can block up to 1000V at 500°C junction and show improvements over traditional organic dielectric options (e.g. Epoxy, Silicone, Polyimide).

Power Semiconductor Devices and Packages: Solder Mechanical Characterization and Lifetime Prediction

Solder reliability is a key aspect for the packaging of low voltage power semiconductor device. The interconnections among package components, e.g. the silicon chip and copper leadframe, and between package itself and the external printed control board (PCB) should be properly designed to ensure the automotive durability requirements. In this framework, the proposed paper introduces an experimental-numeric characterization flow with the purpose to analyze solder visco-plasticity and fatigue during passive temperature cycle. The presented methodology has included solder mechanical characterization aimed to determine the parameters of Anand model which reproduces the solder visco-plastic behavior and the mechanical properties' temperature dependency. Finite element model has been employed to calculate the inelastic work which solder dissipates during each temperature cycle. Simulation results serve as input to predict solder lifetime according to an energetic method. Moreover, failure analyses have been performed to assess the failure mechanism and to check model correlation in terms of number of cycles to failure forecast.

A Study of Thermal Resistance for Surface Mount Type Power Semiconductor Packages

A Study of Thermal Resistance for Surface Mount Type Power Semiconductor Packages

Exploiting Distinct Thermal Response Properties for Power Semiconductor Module Health Monitoring

This article develops the techniques for actively tracking response shifts, induced by thermal–mechanical degradation over components lifetimes’, in spatiotemporal thermal response dynamics. The methodology considers both boundary (e.g., cooling) and internal (e.g., voiding) sources of degradation, and it is considered in the context of power semiconductor devices and packages, including power modules. This article quantifies the transient thermal response sensitivity to degradation using electrothermal impedances viewed with key frequency response function (FRF) metrics over wide dynamic ranges. A developed sensitivity analysis is applied using models and experimental evaluation to relate temperature sensing spatial location, harmonic content of semiconductor device losses, and source of degradation in terms of normalized FRFs that are rapidly interpreted. Complementary loss model parameter sensitivity analysis reveals the advantages in tracking variation in thermal FRF phase delay, rather than amplitude. Finally, to complement pure-FRF approaches for sensing degradation, which use nonparametric data, a method for directly estimating degradation-sensitive physical parameters, in real time, is developed. Experiments demonstrate the automatic estimation of a thermal resistance parameter.

Thermophysical Properties of Zirconia Toughened Alumina Ceramics with Boron Nitride Nanotubes Addition

The demand for high thermal conductivity substrates with electrically insulating materials are increasing with the emerging markets in power electronics and mobile telecommunication device packages. Effective heat transfer in those packages is important to provide high performance and reliability of the product. This paper mainly presents the thermophysical properties of zirconia toughened alumina ceramics with the addition of small amount of boron nitride nanotubes (BNNTs). The effects of the boron nanotubes addition on the sintering behavior, the microstructure and the thermal properties of the yttria-stabilized zirconia toughened alumina (YZTA), nanocomposite ceramics are investigated. The addition of 0.3 wt% boron nitride nanotubes into the YZTA matrix enhanced the thermal diffusivity as well as a mechanical strength. Above all, the addition of boron nitride nanotubes greatly decreased the coefficient of thermal expansion (CTE) of the composites in which the CTE of pure alumina increases with increasing temperatures. Moreover, the BNNTs added YZTA composites revealed a drastic decrease in CTE at high temperature range, 400–800 °C. This enhanced thermal stability of YZTA–BNNT composites may have a potential application to the high temperature structural ceramics and high power semiconductor packaging substrate.

Unified experimental method on fatigue of bonding materials for power semiconductor packaging

Unified experimental method on fatigue of bonding materials for power semiconductor packaging

Effects of Die-Attach Voids on the Thermal Impedance of Power Electronic Packages

Thermal runaway is among the major failure mechanisms of power semiconductor packages. Thermal dissipation of power electronics depends on the quality of the solder die-attach, any defects such as voids, and delamination-impede heat dissipation that results in hot spots that can cause thermal runaway and/or a premature device failure. Therefore, investigation of thermal impact due to die-attach defects is indispensable for improved device performance and reliability. In this paper, transient dual interface measurement is used to characterize the thermal path of a power electronic package consisting of an insulated gate bipolar transistor (IGBT) and copack diode. The die-attach defects were identified by X-ray imaging. The impact of voids on thermal dissipation was quantified by junction-to-case thermal resistance and structure function analysis. The junction-to-case thermal resistance (IGBT) values were found to be increasing with the increase in void%. The largest void% instead of the total void% has a greater impact on the thermal dissipation of the devices. However, die-attach voids under the IGBT die have no impact on junction-to-case thermal resistance (diode), suggesting that the copack diode heat path is independent of the IGBT heat path.

In-Service Diagnostics for Wire-Bond Lift-off and Solder Fatigue of Power Semiconductor Packages

Wire-bond lift-off and Solder fatigue are degradation mechanisms that dominate the lifetime of power semiconductor packages. Although their lifetime is commonly estimated at the design stage, based on mission profiles and physics-of-failure models, there are many uncertainties associated with such lifetime estimates, emerging, e.g., from model calibration errors, manufacturing tolerances, etc. These uncertainties, combined with the diverse working environments of power semiconductor packages result in inaccurate lifetime estimates. This paper presents an approach for estimating the extent of degradation in power semiconductor packages based on online monitoring of key parameters of the semiconductor, namely, the thermal resistance $R_{{\rm{thja}}}$ and the electrical resistance $R_{{\rm{CE}}}$ . Using these two parameters, solder fatigue and wire-bond lift-off can be detected during normal converter operation. In order to estimate these two parameters, two techniques are introduced: a residual obtained from a Kalman filter, which estimates the change in the thermal resistance $R_{{\rm{thja}}}$ , and a recursive least squares algorithm, which is used to estimate the electrical resistance. Both methods are implemented online and validated experimentally.

A Transient Liquid Phase Sintering Bonding Process Using Nickel-Tin Mixed Powder for the New Generation of High-Temperature Power Devices

A transient liquid phase sintering (TLPS) bonding process, Ni-Sn TLPS bonding was developed for the new generation of power semiconductor packaging. A model Ni/Ni-Sn/Ni sandwiched structure was assembled by using 30Ni-70Sn mixed powder as the reactive system. The results show that the bonding layer is composed of Ni3Sn4 and residual fine Ni particles with a small amount of Ni3Sn2 at 340°C for 240 min, which has a heat-resistant temperature higher than 790°C. The microstructural evolution and thermal characteristic of the bonding layer for various times at 300°C and 340°C were also studied, respectively. This reveals that, after isothermally holding for 240 min at 300°C and for 180 min at 340°C, Sn has been completely transformed into Ni-Sn intermetallic compounds (IMCs) and the bonding layer is mainly composed of Ni3Sn4 and residual Ni particles. The analysis result for the mechanical properties of the joint shows that the hardness of the bonding layer at 340°C for 240 min is uniform and that the average value reaches 3.66 GPa, which is close to that of the Ni3Sn4 block material. The shear test shows that, as the holding time increases from 60 min to 180 min at 340°C, because of the existence of Sn, the disparity of shear strength between room temperature and 350°C is large. But when the holding time is 180 min or longer, Sn has been completely transformed into Ni-Sn IMCs. Their performances are very similar whether at room temperature or 350°C.

Electroless Deposition of Fe-Ni Alloy Thin Films for Power Semiconductor Package

Next generation power semiconductor such as silicon carbide (SiC) and gallium nitride (GaN) are known to have an excellent operation characteristic at high temperatures. The high temperature operation needs the power semiconductor package capable of withstanding greater thermal stress. The package for these devices requires a metallization process producing films with low coefficients of thermal expansion (CTEs) matching with the semiconductor and insulating substrates such as ceramics. The metallization by a wet process is expected to be beneficial because of its higher throughput and lower cost than that by dry and high temperature processes. Especially, electroless plating process is of current interest because it is also possible to form films metallized on non-conductive material such as an insulating substrate. Pyrometallurgically produced Fe-Ni alloys with 55 to 70 wt% Fe contents exhibited low CTEs. Therefore, electroless Fe-Ni alloy deposits can be also expected to have low CTEs comparable with those of semiconductor and insulating substrates used in power semiconductor devices. Although the literature contains several reports[1-3] that address the Fe-Ni alloys electrodeposition, the electroless Fe-Ni alloy deposition have not been sufficiently explored. In this study, we preliminary investigated the effect of electroless deposition condition on the alloy compositions, deposition rate, and morphologies of the electoless Fe-Ni alloy deposits. The optimum bath composition for electroless Fe-Ni alloy deposition was as follows: FeSO4 (0~0.02 mol/L), NiSO4(0.03~0.05 mol/L), potassium citrate (0.1 mol/L), potassium pyrophosphate (0.005 mol/L), and dimethylamine borane (0.025 mol/L). The bath temperature was 343 K and the bath pH was adjusted to pH 10.0. In the case of a pretreatment with Pd catalyst, although Fe-Ni alloy deposits were able to be deposited on a Cu substrate, the deposition rate was not enough. Therefore, the Fe-Ni alloy deposits were deposited on the Cu substrate connected with Al sheets to accelerate the deposition rate[4]. Fig. 1 shows effect of Fe2+/ (Fe2++Ni2+) concentration on alloy composition of electroless Fe-Ni alloy deposits and deposition rate for 1 h. The alloy composition was measured by EPMA. With increasing Fe2+/ (Fe2++Ni2+) concentration, Fe contents linearly increased to approximately 70 wt% and Ni contents linearly decreased to approximately 30 wt%. The B contents decreased with increasing Fe2+ concentration and were less than 1 wt% at Fe2+/ (Fe2++Ni2+) concentration of 0.2 or above. The deposition rate gradually decreased from 1.1 to 0.4 μm/h with increasing Fe2+ concentration. The appearance of the all deposits was smooth and uniform. The electroless Fe-Ni alloy deposits with from 0 to 40 wt% Fe contents exhibited bright, whereas those with Fe contents of 60 wt% or above exhibited dull gray. Fig. 2 shows FE-SEM images of the electroless Fe-Ni alloy deposits obtained for 1 h. The all deposits did not have any cracks. The primary particle size increased from several nm to approximately 50 nm with increasing Fe contents. The secondary particle size of all deposits was approximately 100 nm. In conclusion, the Fe-rich Fe-Ni alloy deposits with maximum Fe contents 70 wt% were obtained using dimethylamine borane as a reducing agent by electroless plating process; the electroless Fe-Ni alloy plating process may become an attractive metallization process for power semiconductor package. Acknowledgement This work was partially supported by the Kyoto Technoscience Center and Industry-Academia Collaborative R&D Programs “Super Cluster Program” (JST).

Non-Pressure Joining Method for Zn-Al Solder by Pre-Ultrasonic Bonding

Introduction In this paper, we propose non-pressure soldering method during reflow process for Zn-Al solder by breaking oxide film on its surface in advance of heating. SiC power semiconductors can operate at a temperature of 200 °C or more. The temperature difference between junction of the semiconductors and ambient air makes effective heat dissipation, therefore the cooling system that occupies a large volume in an semiconductor power module can be minimized. If we use these advantages, we have to use high melting point solder such as Zn-Al alloy solder. But the solder, which is usually provided as preformed sheet, have stiff natural oxide film on its surface, therefore applying pressure to the preformed sheet during reflow process is necessary to break the oxide film for secure soldering. New proposed method don’t need these way. The reflow process becomes simplified. Method and Result Effectiveness of the joining method is described with Fig. 1. This figure shows fracture surfaces of samples after shear test. The samples are attempted to join a circuit pattern and a SiC dummy chip by soldering of Zn-Al preformed solder. The sample (a) is not given ultrasonic bonding before reflow. The preformed sheet of the sample (b) is attached to both the chip and the circuit pattern by ultrasonic bonding in advance of reflow. Then the two samples are heated in the same reflow process and evaluated based on shear test. As a result of the test, The chip of the sample (a) was easily peeled off. On the other hand, shear strength of (b) is 60.4 MPa on average. The reason of different results is described below. Since the natural oxide film was broken by ultrasonic bonding, and a newly formed surface is exposed, the solder and both the chip and the circuit pattern are mutually joined. When the sample is heated, the solder in the preformed sheet melts and overflows from the bonding surface. Therefore the chip and the circuit pattern are joined by soldering. Without breaking oxide film like (a) in advance of reflow, solder joint doesn’t occur. The proposed soldering method has a potential to be low-cost and simple process for packaging of SiC power semiconductors. Acknowledgment This work was supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), "Next-generation power electronics/Consistent R&D of next-generation SiC power electronics", and "the Novel Semiconductor Power Electronics Project Realizing Low Carbon Emission Society" (funding agency: NEDO). Figure 1

Quantification of cracked area in thermal path of high-power multi-chip modules using transient thermal impedance measurement

Transient thermal impedance measurement is commonly used to characterize the dynamic behaviour of the heat flow path in power semiconductor packages. This can be used to derive a “structure function” which is a graphical representation of the internal structure of the thermal stack. Changes in the structure function can thus be used as a non-destructive testing tool for detecting and locating defects in the thermal path. This paper evaluates the use of the structure function for testing the integrity of the thermal path in high power multi-chip modules. A 1.2kV/200A IGBT module is subjected to power cycling with a constant current. The structure function is used to estimate the level of disruption at the interface between the substrate and the baseplate/case. Comparison with estimations of cracked area obtained by scanning acoustic microscopy (SAM) imaging shows excellent agreement, demonstrating that the structure function can be used as a quantitative tool for estimating the level of degradation. Metallurgical cross-sectioning confirms that the degradation is due to fatigue cracking of the substrate mount-down solder.