Power-off State Research Articles

An Estimation Method of High-Order LC Circuits in Power Electronic Converters

This paper proposes a parameter estimation method for high-order LC circuits conducted during the power-OFF of power electronic converters. It is based on a battery-powered compact signal injection unit and a circuit modeling method to estimate the LC circuit parameters. The proposed method aims for LC component condition monitoring in applications with routine-based maintenance or frequent ON/OFF operation (e.g., wind power, photovoltaic, traction systems). Compared to LCR meters and impedance analyzers, the proposed method has a significantly lower implementation cost and does not require disassembly of components. Moreover, it is a converter-level method in which the signal injection unit only needs to connect the converter inputs or outputs. Compared to power-ON LC parameter estimation methods, the proposed one is non-invasive without adding any hardware or software algorithm that may introduce new risks to converter operation. This method can handle the converters with high-order LC structures (e.g., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$2^{nd}$</tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$4^{th}$</tex-math></inline-formula> -order) in converter power-OFF state, which has not been achieved by existing power-OFF solutions. Therefore, the proposed method is promising for the specific applications of interest mentioned above. The parameter estimation algorithm and signal injection unit design are presented. The experimental results indicate that the estimation errors of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$2^{nd}$</tex-math></inline-formula> -order equivalent circuit, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$3^{rd}$</tex-math></inline-formula> -order equivalent circuit, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$4^{th}$</tex-math></inline-formula> -order equivalent circuit are lower than 1.6%, 2.5%, and 3%, respectively. The estimated LC parameters can be further used as inputs for operation optimization or condition monitoring of the converters.

Research on the mechanism and control methods of mechanical drift in linear ultrasonic motors

Linear ultrasonic motors (LUMs) have advantages such as de-energized self-locking and micro-nano displacement resolution. However, their positioning and control accuracy are negatively affected by mechanical drift, which limits their application in ultra-precision fields. To date, the quantitative mechanism of LUM mechanical drift under power-off conditions remains unreported. To solve the problem, we employ the creep theory to identify the clamp stiffness parameters and consider the internal friction and stick-slip effects of the slider, thereby establishing a non-autonomous dynamic model of the LUM mechanical drift in the power-off state. Subsequently, we utilize this model to investigate how the LUM’s structural parameters influence mechanical drift and explore methods to mitigate this undesirable phenomenon. Finally, we validate the model’s validity through experimental research. Our findings reveal that structural creep is the primary cause of mechanical drift in LUMs. Increasing the tangential stiffness of the clamp component and slider internal friction proves to be an effective approach to reducing mechanical drift. This study holds substantial theoretical and practical significance as it deepens understanding of the mechanisms of mechanical drift in LUMs and offers a pathway to achieve effective mechanical drift control.

Measurement of Radiation Absorbed Dose Effects in SRAM-Based FPGAs

As of now, SRAM-based FPGAs are mainly preferred in the non-safety applications of NPPs. If the susceptibility to radiation effects of SRAM-FPGAs improves further, then the reliability of the applications can be improved. This experimental study investigates the radiation absorbed dose effects in SRAM-based FPGAs. The irradiation experiments have been conducted by keeping the device in both the power-on and power-off states inside a gamma radiation chamber of Co-60 source. In some applications, the device is deployed in the radiation environments and remains in the power-off condition for substantial period. At the time of need, the device may not function properly as demanded by the system due to the cumulative dose effect on SRAM-based FPGA. So the study of irradiation experiments on SRAM-FPGAs in the power-off state has its significant importance the same as the power-on state. The power supply current variation and the functionality failure of the device are monitored in both cases. In the power-on test, the device is configured with particular functionality and the parameters are measured continuously, but in the power-off test, the performance variations of the device are captured after configuring the device at particular time intervals during the course of the experiment. Along with the power supply current variation, we used an indirect method of measuring the propagation delay based on ring oscillator implementation. The device has been irradiated up to a dose level of 2.5 Mrad in power-on test and up to 50 Mrad in the power-off test.

Ultra-fast data sanitization of SRAM by back-biasing to resist a cold boot attack

Although SRAM is a well-established type of volatile memory, data remanence has been observed at low temperature even for a power-off state, and thus it is vulnerable to a physical cold boot attack. To address this, an ultra-fast data sanitization method within 5 ns is demonstrated with physics-based simulations for avoidance of the cold boot attack to SRAM. Back-bias, which can control device parameters of CMOS, such as threshold voltage and leakage current, was utilized for the ultra-fast data sanitization. It is applicable to temporary erasing with data recoverability against a low-level attack as well as permanent erasing with data irrecoverability against a high-level attack.

Effect analysis on integration efficiency and safety performance of a battery thermal management system based on direct contact liquid cooling

• An engineered battery system based on direct contact liquid cooling is developed. • The system has excellent thermal management performance. • Direct contact liquid cooling can efficiently and quickly dissipate heat. • The system can effectively inhibit the TR propagation in the power-off state. • No tube can get a higher degree of integration. We design and fabricate a novel lithium-ion battery system based on direct contact liquid cooling to fulfill the application requirement for the high-safety and long-range of electric vehicles. By the immersion in the flowing silicone oil to achieve the highly efficient heat exchange, the NCM811 cells can be grouped without gap, and thereby the battery system achieves maximum volume efficiency. The mass and volume integration ratio of the battery system are 91% and 72%, respectively, which are 1.1 and 1.5 times that of the tube-based indirect liquid contact cooling system, respectively. Specifically, the temperature increment of the cells during 1C discharge does not exceed 13 ℃, and the dynamic temperature difference is less than 8.8 ℃. The results from simulation show that the maximum temperature rise and maximum temperature difference of the direct contact liquid cooling system are only 20%–30% of the indirect contact liquid cooling system. Particularly, the system can effectively prevent the thermal runaway propagation without any additional measures, owing to the high heat dissipation rate and oxygen isolation. The research has led to the successful construction of an oil-immersed battery system with high integration ratio and excellent safety, which provides a feasible solution for the demand of the high safety and high specific energy of the electric vehicle battery system.

Optical Wake-Up From Power-Off State for Autonomous Sensor Nodes

Wireless sensor nodes spend most of their time in standby mode and wake up periodically to send measurement data. Typically, a radio-frequency antenna is coupled with an amplifier to provide this wake-up function; together, these two elements recognize instances of radio signal activation. Even during standby operation, the sensor node utilizes a certain base amount of energy, which can be critical when using an energy-harvesting source. In this study, we propose a novel optical approach to the wake-up function for autonomous sensor nodes, which employs a solar cell as the wake-up signal detector. A bright light flash coming from another node or a smartphone hits a solar cell and activates the sensor node. Unlike photodiodes or RF-antennas, solar cells do not require any additional energy to detect such a signal. Therefore, the proposed electrical circuit allows the sensor node to wake-up from a complete power-off state. The solar cell of the novel wake-up receiver has an area of sensitivity of 8 mm × 10 mm. The wake-up signal can be recognized from a maximum distance of 25 cm at a range of ambient illumination from 0 - 1600 lx with a transmitter optical power of 20 mW. In the power-off state, the power consumption of this novel design is the lowest of all existing off-the-shelf wake-up receivers: 248 pW at 0 lx and 627 nW at 1600 lx.

Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices

Switching lattices are two-dimensional arrays composed of two or four-terminals switches organized as a crossbar array. The idea of using regular two-dimensional arrays of switches for Boolean function implementation was proposed by Akers in 1972. Recently, with the advent of a variety of emerging nanoscale technologies, lattices have found a renewed interest. Emerging technologies allow more complex function integration, thanks to their smaller sizes and advanta geous properties such as zero leakage current, capability to retain data when in power-off state, and almost unlimit edendurance, to name just a few appealing features. Also, implementation of new computing paradigms combining memory and logic becomes possible. However, emerging technologies show a non-negligible defect ratio and higher sensitivity to process and environment variations. The reliability challenges in adopting these technologies need to be investigated. In this paper, we analyze the resilience of switching lattices to stuck-at-fault model (SAF). We first identify the critical switches through an elaborated sensitivity methodology and extensive analysis of the lattice. Next, we propose several techniques to improve lattice resilience in the face of these types of faults, that can be implemented after lattice logic optimization steps.

Cloud evidence tracks of storage service linking with iOS systems

The increasing usage of mobile cloud computing leads the cloud to become a hotbed of crime. Cloud storage is different from previous data storage in digital forensics. In this paper, we concentrate on gathering evidence from mobile iOS devices and the types of data remnants that can be found on iOS devices for different user scenarios and device states. We develop several steps for experimenting on Google Drive, OneDrive and Dropbox. We found that the evidence collection of power-off state is not the major problem in digital forensics. Different applications of cloud storage show the different statuses of data remnants. The study also shows that thumbnails and cache files are the key of evidence recovery. We present how the digital investigators to collect evidence by examining the data remnants files as well.

Magnetically Steered Robotic Insertion of Cochlear-Implant Electrode Arrays: System Integration and First-In-Cadaver Results.

Cochlear-implant electrode arrays (EAs) must be inserted accurately and precisely to avoid damaging the delicate anatomical structures of the inner ear. It has previously been shown on the benchtop that using magnetic fields to steer magnet-tipped EAs during insertion reduces insertion forces, which correlate with insertion errors and damage to internal cochlear structures. This paper presents several advancements toward the goal of deploying magnetic steering of cochlear-implant EAs in the operating room. In particular, we integrate image guidance with patient-specific insertion vectors, we incorporate a new nonmagnetic insertion tool, and we use an electromagnetic source, which provides programmable control over the generated field. The electromagnet is safer than prior permanent-magnet approaches in two ways: it eliminates motion of the field source relative to the patient's head and creates a field-free source in the power-off state. Using this system, we demonstrate system feasibility by magnetically steering EAs into a cadaver cochlea for the first time. We show that magnetic steering decreases average insertion forces, in comparison to manual insertions and to image-guided robotic insertions alone.

DC and analogue/radio frequency performance optimisation of heterojunction double‐gate tunnel field‐effect transistor

The electrostatic behaviour of the different configurations of n-type heterojunction double-gate tunnel field-effect transistor (HDGTFET) has been analysed. The analysis is based on the basics of the circuit elements such as drain current, transconductance, parasitic capacitances, cut-off frequency and gain bandwidth product. From the investigation carried out, it can be inferred that dual metal hetero-dielectric double-gate HDGTFET with gate underlap achieves both low standby power OFF state current and high performance at low supply voltage. The performance of the device having different configurations has been analysed for drain region having a uniform and Gaussian doping profile.

Low Store Power, High Speed, High Density, Nonvolatile SRAM Design with Spin Hall Effect-Driven Magnetic Tunnel Junctions

As static power caused by leakage currents has become a critical challenge for the CMOS technology power-gating techniques, which employ nonvolatile data retention circuits, e.g., nonvolatile static random-access memory (NV-SRAM) are expected to efficiently solve this challenge. One of the key features of NV-SRAM is to utilize nonvolatile devices, such as resistive RAM, phase change memory, and magnetic tunnel junction (MTJ), to store the runtime data when system is in the standby power-off state. Among them, MTJ-based NV-SRAM is widely considered as the most potential candidate in high-speed, low-power, and high-reliability applications, thanks to the advantageous features of the MTJ devices, such as fast data store/restore operation, low critical writing current density, and high endurance. In this paper, we propose a novel NV-SRAM design with spin Hall effect (SHE)-driven MTJ devices. In specific, two embodiments are designed based on the magnetic anisotropy property (i.e., in-plane or perpendicular) of the MTJ device. Using our previously developed SHE-MTJ model and a CMOS design kit, circuit operation and performance of the proposed NV-SRAM designs were demonstrated at the 40-nm technology node. Simulation results show that our proposed NV-SRAM design achieves performance improvement in terms of power, delay, and area, compared with conventional designs.

Reducing the system standby power of a personal computer

Most previous low-power personal computer designs have been either focused on power efficiency improvement or on software power management in the working states. This research aims to reduce the total standby power amount in the off state. The authors accomplish the goal of reducing the power consumption by a wake-up device which is replaced by a chip with a still lower consumption. The authors redesign the power circuit and cut off the power supply for the unnecessary chips, with the exception of the power needed for the specific chip used to wake up the system. The authors also turn off the power supply of the original power controller chip which is used to control the system's power status. In addition, the authors use another low-power chip instead of the original one and redesign the power sequence of the system in order to maintain the system's power state while the system's power status controller is turned off. Finally, as the authors use this low-power chip to manage the standby power source separately by means of the remote wake-up devices, the authors reduce further the standby power consumption to 4.4 mW in the power-off state by use of the various wake-up methods. The total result is an improvement of approximately 99.3%.

The Design of Cable Anti-Theft System for the Streetlight of Urban

To solve the problem of repeated loss of low voltage power cables, this paper designed a project in preventing the cables from stealing. The design of the system is based on the Impedance Characteristics method which is used in power-on state and the Parallel Resonance which is used in power-off state. The paper describes the principle of the method and how to combine the two methods. The simulation and test for it show that the method is correct. The system makes it possible to protect the cable from stealing without affecting the electricity system. In addition, it can calculate the fault location. The system has better accurateness and stableness than the common cable anti-theft system.

A bistable shape memory microswitch with high energy density

A novel concept and various layouts of a bistable microswitch are presented,that combine an antagonistic shape memory alloy (SMA) actuation mechanismwith two end positions, and magnetic components to maintain the endpositions in the power-off state. The antagonistic SMA actuation mechanismconsists of two mechanically coupled freely suspended TiNi microbridges of 20 µm thickness that are pre-strained with respect to each other. The electro-thermo-mechanicalresponse of the coupled microbridges is investigated for various degrees of pre-strain todetermine the maximum actuation stroke, minimum required magnetic retention force andmaximum switching force. Different layout variants consisting of hard- and soft-magneticmicrostructures are compared and evaluated for magnetic retention. The optimization ofthe ferromagnetic attraction force of a specific layout is shown by finite elementsimulations. First demonstrator microswitches with outer dimensions of about7 × 7 × 4 mm3 are presented that show large work outputs featuring strokes and contact forces up to 84 µm and 30 mN, respectively.

A silicon electrothermal rotational micro motor measuring one cubic millimeter

A micro machined single crystal silicon micro motor has been developed that uses electrothermal actuators and micro assembly. The entire motor system occupies one cubic millimeter and can be integrated into a variety of packages. Four electrothermal bent-beam actuators in the stator drive the 290 µm diameter 50 µm thick rotor through friction-based contact. Flexures between the actuators and contact points step the rotor less than one degree with each driving waveform cycle; the motor can achieve 7.3 rpm. Since the micro motor is assembled it resists rotation in a power-off state and drives with 0.14 µN m of torque. Details on the design, assembly and operation of the device are included. Finite element analysis has been applied to model the electrothermal transient response and achieve an 81% improvement in efficiency with 24 V pulse driving signals. The 1.2 mm by 1.2 mm by 0.7 mm device has been shown to rotate a 100 µm diameter tungsten probe within the confines of a SEM.

Rapid power cycling of flip-chip and CSP components on ceramic substrates

Power cycling has been done for flip-chip and CSP components solder joined onto ceramic substrates. Cycle periods as short as 1 min were applied in the experiments where the chip temperature varied between about 30°C in the power off-state and 100–150°C in the power on-state. Disconnections of the joints were found after 4000–17000 power cycles. The flip-chip components joined onto low temperature cofired ceramic substrate showed slightly better reliability than the components joined onto alumina substrate. Most of the samples showed clear effects of deterioration of the joints seen as increasing chip temperature for power on-state. The experimental results are compared with calculations based on modified Coffin–Manson equation as well as with one-dimensional simulations.