Ultra-fast data sanitization of SRAM by back-biasing to resist a cold boot attack

Seong-Joo Han,Yang-Kyu Choi,Ji-Man Yu,Joon-Kyu Han,Mun-Woo Lee,Gyeong-Jun Yun

doi:10.1038/s41598-021-03994-2

Seong-Joo Han, Yang-Kyu Choi + Show 4 more

Open Access

https://doi.org/10.1038/s41598-021-03994-2

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Abstract

Although SRAM is a well-established type of volatile memory, data remanence has been observed at low temperature even for a power-off state, and thus it is vulnerable to a physical cold boot attack. To address this, an ultra-fast data sanitization method within 5 ns is demonstrated with physics-based simulations for avoidance of the cold boot attack to SRAM. Back-bias, which can control device parameters of CMOS, such as threshold voltage and leakage current, was utilized for the ultra-fast data sanitization. It is applicable to temporary erasing with data recoverability against a low-level attack as well as permanent erasing with data irrecoverability against a high-level attack.

Highlights

Static random access memory (SRAM) is a well-established type of volatile memory, data remanence has been observed at low temperature even for a power-off state, and it is vulnerable to a physical cold boot attack
When positive VBS was forwardly applied to the NMOS of the left inverter and negative VBS was forwardly applied to the PMOS of the right inverter with the same magnitude of more than 0.9 V (Fig. 1c), the initial VQ of 0 V was changed to 1 V and the initial VQB of 1 V was changed to 0 V
The latch states in SRAM were distorted by the forward back-biasing in order to reset data or make data unreadable against hacking

Summary

Introduction

SRAM is a well-established type of volatile memory, data remanence has been observed at low temperature even for a power-off state, and it is vulnerable to a physical cold boot attack. A few approaches were demonstrated to prevent SRAM data from being decoded by the physical cold boot attack by use of additional circuitry including an erase transistor, storage capacitor, and charge pump. They sacrificed layout efficiency and increased hardware c ost[8,9]. The other is permanent erasing by asymmetric application of back-bias to a PMOS in one inverter and to an NMOS in the other inverter In the former case, data recovery is allowed after a low-level threat attempt by hacking. The results show that the proposed back-bias scheme can provide immunity against a cold boot attack at low temperature

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Conclusion