Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices

Abstract

Switching lattices are two-dimensional arrays composed of two or four-terminals switches organized as a crossbar array. The idea of using regular two-dimensional arrays of switches for Boolean function implementation was proposed by Akers in 1972. Recently, with the advent of a variety of emerging nanoscale technologies, lattices have found a renewed interest. Emerging technologies allow more complex function integration, thanks to their smaller sizes and advanta geous properties such as zero leakage current, capability to retain data when in power-off state, and almost unlimit edendurance, to name just a few appealing features. Also, implementation of new computing paradigms combining memory and logic becomes possible. However, emerging technologies show a non-negligible defect ratio and higher sensitivity to process and environment variations. The reliability challenges in adopting these technologies need to be investigated. In this paper, we analyze the resilience of switching lattices to stuck-at-fault model (SAF). We first identify the critical switches through an elaborated sensitivity methodology and extensive analysis of the lattice. Next, we propose several techniques to improve lattice resilience in the face of these types of faults, that can be implemented after lattice logic optimization steps.