Power Metal Oxide Semiconductor Research Articles

4H-SiC/SiO2 Interface Degradation in 1.2 kV 4H-SiC MOSFETs due to Power Cycling Tests

Power cycling tests (PCTs) assess the reliability of power devices by closely simulating their operating conditions. A PCT was performed on commercially available 1.2 kV 4H-SiC power metal–oxide–semiconductor field-effect transistors to observe its impact on the 4H-SiC/SiO2 interface. High-resolution transmission electron microscopy and electron energy loss spectroscopy measurements showed variations in the length of the 4H-SiC/SiO2 transition layer, depending on whether the device was power cycled. Moreover, the total resistance at Vg >> Vt in Rtot − (Vg-Vt)−1 graph increased to 16.5%, while it changed more radically to 47.3% at Vg ≈ Vt. The threshold voltage shifted negatively. These variations cannot be expected solely through the wearout of the package.

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

Refined Analysis of Leakage Current in SiC Power Metal Oxide Semiconductor Field Effect Transistors after Heavy Ion Irradiation

A leakage current is the most critical parameter to characterize heavy ion radiation damage in SiC MOSFETs. An accurate and refined analysis of the source and generation process of a leakage current is the key to revealing the failure mechanism. Therefore, this article finely tests the online and post-irradiation leakage changes and leakage pathways of SiC MOSFETs caused by heavy ion irradiation, analyzes the damaged location of the device in reverse, and discusses the mechanism of leakage generation. The experimental results further confirm that an increase in the leakage current of a device during heavy ion irradiation is positively correlated with the applied voltage of the drain, but the leakage path is not direct from the drain to the source. The experimental analysis of the source of the leakage current of the device after irradiation indicates that there is also a leakage current path between the device gate and source. The research results suggest that the experimental sample is more prone to a single-event gate rupture effect under this heavy ion radiation condition. The gate breakdown mainly occurs in the gate oxide layer at the neck region. This research can provide a theoretical basis for the radiation resistance reinforcement of SiC power devices.

Charge pumping electrically detected magnetic resonance of silicon carbide power transistors

Silicon carbide (SiC) power devices are becoming central components in high voltage electronics. However, defects at interfaces and in the bulk continue to severely impact their reliability and performance. Here, we develop a charge pumping method to characterize SiC/SiO2 interface defects in fully fabricated commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The method is then used to address spin states at the SiC/SiO2 interface via charge pumping electrically detected magnetic resonance (CP-EDMR). We apply these methods to investigate the power MOSFET after electron irradiation over a dose range of 1013−1017 cm−2. We finally discuss CP-EDMR as a technique to interrogate spins during device operation for real-time monitoring of the device quality, performance, and degradation and as a probe for local magnetic fields.

Comparison of the Performance-Degrading Near-Interface Traps in Commercial SiC MOSFETs

This paper presents a comparison of the density of performance-degrading near-interface traps (NITs) in the most commonly available 1200 V commercial N-channel SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). A recently developed integrated-charge technique was used to measure the density of NITs with energy levels aligned to the conduction band, which degrade MOSFET’s performance by capturing and releasing electrons from the channel biased in the strong-inversion condition. Trench MOSFETs of one manufacturer have lower densities of these NITs in comparison to MOSFETs with the planar gate structure, corresponding to observed higher channel-carrier mobility in trench MOSFETs. Different response-time distributions were also observed, corresponding to different spatial location of the measured NITs.

Synergistic effect of total ionizing dose on single-event gate rupture in SiC power MOSFETs

The synergistic effect of total ionizing dose (TID) and single event gate rupture (SEGR) in SiC power metal–oxide–semiconductor field effect transistors (MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.

Analysis of Ruggedness of 4H-SiC Power MOSFETs with Various Doping Parameters

This work investigates the effect of the doping concentration of SiC power metal-oxide–semiconductor field-effect transistors (MOSFETs) under an unclamped inductive switching (UIS) condition. Switching circuits such as inverters and motor-drive circuits often face unexpected operating conditions; therefore, a UIS test is performed to assess the avalanche ruggedness of the device, and design parameters such as the doping concentration should be considered to improve the UIS characteristics. Technology computer-aided design circuit simulation results, such as the current flows during failure and electrical changes, were obtained by changing the doping concentration of each region in the SiC power MOSFET.

Degradation Behavior and Mechanism of SiC Power MOSFETs Under Repetitive Transmission Line Pulse Stress

The electrostatic discharge robustness of silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) are investigated by the transmission line pulse (TLP) method. The degradation behavior of key electrical parameters of the device under repetitive TLP stress is investigated. A decrease in threshold voltage, an increase in gate leakage current, and the degradation of gate capacitance parameters are observed compared with the prestress values. Low-frequency noise (LFN) test results show that after multiple TLP stress cycles, the typical leakage current noise of the device increases by approximately one order of magnitude compared to prestress, which means that the trap density extracted based on the McWhorter model increases by one order of magnitude after 1000 TLP stress pulses. Furthermore, sources of defects in the gate oxide dielectric of the devices after stresses are analyzed. The physical mechanism of the changes of SiC MOSFETs characteristics could be attributed to the hole trapping by oxygen vacancy defects and single carbon interstitial in the oxide layer after TLP stresses, which induces an electrostatic effect and results in the changes in the electrical properties of the devices. The results may be useful in the design and application of SiC power MOSFETs.

MEMS based metal oxide semiconductor carbon dioxide gas sensor

This paper describes the design and development of low power Micro Electro Mechanical Systems (MEMS) microheater and metal oxide semiconductor CO 2 sensor. To achieve low power, suspended plasma enhanced chemical vapour deposited SiO 2 diaphragm is used. BaTiO 3 -CuO is considered as metal oxide doped with 1% Ag and will be used as a sensing material to sense the CO 2 gas. To get the required temperature for the sensing film, three different metals namely, Platinum (Pt), Titanium (Ti) and Tungsten (W) are simulated by using COMSOL Multiphysics 5.6. The proposed microheater structure is shown to have a good temperature consistency throughout the heater's active region while consuming low power. The microheater geometry of 100 μm × 100 μm with its electro-thermal temperature results is presented here. For an applied voltage, we report a maximum average temperature of Pt i.e. ∼99.51%, Ti ∼ 97.12% and W ∼ 89.78% for 300 °C respectively. Fabrication of CO 2 sensor along with MEMS microheater had been designed and demonstrated. Energy consumed by the proposed platinum microheater geometry is 4.8 mW at 250 °C and 5.8 mW at 300 °C. The sensitivity characteristic is based on resistance sensing which has been found to be 21% for 400 ppm CO 2 gas concentration and 70% for 1000 ppm. Comparatively capacitive based sensitivity is found to be ~54% for 400 ppm and 95% for 1000 ppm. MOS Capacitive based Gas Sensor Model • Carbon dioxide has traditionally been recognized as one of the most serious atmospheric pollutants • Industries, Agriculture, Home safety and healthcare expands the marketplace for miniaturised, inexpensive gas sensors • Low power, reliable and cost-effective metal oxide semiconductor (MOS) based CO2 sensors are desirable • Sensitivity and Selectivity parameters play a very important role in designing gas sensors • Designing a microheater geometry is of great importance to achieve a preferred temperature uniformity and overall performance of a metal oxide semiconductor sensor

Gate Stress Polarity Dependence of AC Bias Temperature Instability in Silicon Carbide MOSFETs

As the silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistor (MOSFET) develops, increasing efforts are placed on ac bias temperature instability (AC BTI). It was reported that AC BTI becomes significant when and only when the gate stress is bipolar. A detailed study is made in this article to reveal the underpinning mechanism. A physical model is proposed to explain on how and why the gate stress bipolar affects the threshold drift. It is found that the gate stress polarity has to be carefully defined. As the model shows, it is the bipolar electric field, rather than the gate voltage itself, that speeds up the threshold voltage drift. It is hoped that this study provides a stepping stone toward the eventual understanding and management of AC BTI.

A Figure of Merit for Selection of the Best Family of SiC Power MOSFETs

This paper proposes a criterion to select the best family of commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs) that provides the highest quality and reliability. Applying a recently published integrated-charge method, a newly proposed figure of merit is correlated to the density of near-interface traps that degrade the quality and reliability of SiC MOSFETs. The applicability of the proposed figure of merit is experimentally demonstrated with the most widely used and commercially available planar and trench MOSFETs from different manufacturers.

High reactivity of H2O vapor on GaN surfaces

ABSTRACT Understanding the process of oxidation on the surface of GaN is important for improving metal-oxide-semiconductor (MOS) devices. Real-time X-ray photoelectron spectroscopy was used to observe the dynamic adsorption behavior of GaN surfaces upon irradiation of H2O, O2, N2O, and NO gases. It was found that H2O vapor has the highest reactivity on the surface despite its lower oxidation power. The adsorption behavior of H2O was explained by the density functional molecular dynamic calculation including the spin state of the surfaces. Two types of adsorbed H2O molecules were present on the (0001) (+c) surface: non-dissociatively adsorbed H2O (physisorption), and dissociatively adsorbed H2O (chemisorption) molecules that were dissociated with OH and H adsorbed on Ga atoms. H2O molecules attacked the back side of three-fold Ga atoms on the (0001̅) (−c) GaN surface, and the bond length between the Ga and N was broken. The chemisorption on the (101̅0) m-plane of GaN, which is the channel of a trench-type GaN MOS power transistor, was dominant, and a stable Ga-O bond was formed due to the elongated bond length of Ga on the surface. In the atomic layer deposition process of the Al2O3 layer using H2O vapor, the reactions caused at the interface were more remarkable for p-GaN. If unintentional oxidation can be resulted in the generation of the defects at the MOS interface, these results suggest that oxidant gases other than H2O and O2 should be used to avoid uncontrollable oxidation on GaN surfaces.

Effects of high temperature annealing on the atomic layer deposited HfO2/β-Ga2O3(010) interface

Atomic layer deposited HfO2 is a primary candidate for metal–oxide–semiconductor (MOS) power devices based on the ultra-wide bandgap semiconductor β-Ga2O3. Here, we investigated the thermal stability of this stack. Out-diffusion of gallium into HfO2, measured by secondary ion mass spectroscopy depth profile, was observed after annealing at 900 °C. Electrical characterization of MOS capacitors (MOSCAPs) showed that this diffusion caused a dramatic increase in leakage current. For annealing temperatures between 700 and 850 °C, no significant Ga diffusion into the HfO2 layer was observed. Nonetheless, MOSCAPs made with stacks annealed at 700 °C have significantly higher forward bias leakage compared to as-prepared MOSCAPs. Through photo-assisted capacitance–voltage measurements (C–V), we found that this leakage is due to an increase in interface traps (Dit) lying 0.3–0.9 eV below the conduction band. We thus have identified how thermal treatments influence HfO2/Ga2O3 behavior: for anneals at 700–850 °C, we observe an increase in Dit and leakage, while annealing at >900 °C results in notable Ga out-diffusion and a catastrophic degradation in leakage. This understanding is key to improving the performance and reliability of future β-Ga2O3 MOS power devices.

Development of solderable layer on power MOSFET for double-side bonding

The use of power metal oxide semiconductor field effect transistor (MOSFET) packages is being actively explored to improve heat dissipation by fast switching. The double-side cooling package structure of power MOSFETs is considered efficient for heat dissipation, which requires bonding the MOSFET with Cu lead frames on both the top and bottom sides by soldering. Although soldering can typically be performed for the bottom side, it is challenging to perform on the top side due to Al metallization and has, therefore, been rarely reported. In this study, we developed various layers on the top side of a MOSFET to enable soldering between the MOSFET and Cu lead frame to realize a double-side cooling package. After depositing the thin films on the top side of the MOSFET with Ag and Ni materials, we fabricated the double-side package in the form of a TO-263 package to evaluate the electrical characteristics of the power MOSFET. In addition, we fabricated a typical TO-263 package having only the bottom-side cooling structure and compared its performance with that of the double-side cooling structure. Thermal cycle tests were performed up to 1500 cycles for 25 min at each extreme temperature in the −55 to 125 °C range. Electron backscatter diffraction was conducted on Al metallization beneath the solderable layers to analyze the change in the grain orientation and size of the Al layer. In addition, the stress behavior of the Al layer according to the presence of the Ni layer was compared using FEM simulation. Our findings provide the optimal solderable metallization of 600-nm-thick Ni and Ag layers each for bonding on the top layer of a power MOSFET, realizing a double-side cooling package for power MOSFETs.

3C-SiC-on-Si MOSFETs: Overcoming Material Technology Limitations

The cubic polytype (3C-) of silicon carbide (SiC) is an emerging semiconductor technology for power devices. The featured isotropic material properties along with the wide band gap characteristics make it an excellent choice for power metal oxide semiconductor field effect transistors (<small>mosfet</small>s). It can be grown on silicon (Si) substrates which is itself advantageous. However, the allowable annealing temperature is limited by the melting temperature of Si. Hence, devices making use of 3C-SiC on Si substrate technology suffer from poor or even almost negligible activation of the p-type dopants after ion implantation due to the relatively low allowable annealing temperature. In this article, a novel process flow for a vertical 3C-SiC-on-Si <small>mosfet</small> is presented to overcome the difficulties that currently exist in obtaining a p-body region through implantation. The proposed design has been accurately simulated with technology computer-aided design process and device software. To ensure reliable prediction, a previously validated set of material models has been used. Further, a channel mobility physics model was developed and validated against experimental data. The output characteristics of the proposed device demonstrated promising performance, what is potentially the solution needed and a huge step toward the realization of 3C-SiC-on-Si <small>mosfet</small>s with commercially grated characteristics.

Transient Electro-Thermal Coupled Modeling of Three-Phase Power MOSFET Inverter during Load Cycles.

This study introduces an effective and efficient dynamic electro-thermal coupling analysis (ETCA) approach to explore the electro-thermal behavior of a three-phase power metal–oxide–semiconductor field-effect transistor (MOSFET) inverter for brushless direct current motor drive under natural and forced convection during a six-step operation. This coupling analysis integrates three-dimensional electromagnetic simulation for parasitic parameter extraction, simplified equivalent circuit simulation for power loss calculation, and a compact Foster thermal network model for junction temperature prediction, constructed through parametric transient computational fluid dynamics (CFD) thermal analysis. In the proposed ETCA approach, the interactions between the junction temperature and the power losses (conduction and switching losses) and between the parasitics and the switching transients and power losses are all accounted for. The proposed Foster thermal network model and ETCA approach are validated with the CFD thermal analysis and the standard ETCA approach, respectively. The analysis results demonstrate how the proposed models can be used as an effective and efficient means of analysis to characterize the system-level electro-thermal performance of a three-phase bridge inverter.

Single-Event Gate Rupture Hardened Structure for High-Voltage Super-Junction Power MOSFETs

This article presents design for a 650-V super-junction (SJ) power metal–oxide–semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.

Systematic Characterization of Plasma-Etched Trenches on 4H-SiC Wafers.

Silicon carbide power semiconductors overcome some limitations of silicon chips, and therefore, SiC is an attractive candidate for next-generation power electronics. In addition, the number of possible vertical devices that can be obtained on a given surface using the trench technique is significantly larger than that attainable using a planar setup. Moreover, a SiC trench power metal oxide semiconductor field-effect transistor (power MOSFET) structure removes the junction field-effect transistor (JFET) region (that would decrease the current flow width) and improves the channel density, thus reducing the specific electrical resistance. Consequently, in the present study, we report on the chemical bonding state of elements and structural characterization of trenches, obtained using SF6-based plasma etching, on the 4H-SiC polytype substrate. An interferometric algorithm that finds the endpoint to stop etching governed the trench depth. Scanning electron microscopy, transmission electron microscopy, atomic force microscopy, and X-ray photoelectron spectroscopy analyses stated the high quality and uniformity of the trenches. These materials are particularly promising for the fabrication of the SiC MOSFET to be implemented in the manufacturing of power devices.

A Study on the Optimization of Deep-Trench Super Junction Metal Oxide Semiconductor Field-Effect Transistor

Power metal oxide semiconductor field-effect transistor is a switching device designed to handle large power consumption; it enables fast switching, resulting in low power consumption. Power devices are used as important components that determine the operation and performance of electrically powered products such as home appliances, smartphones, and automobiles. Power devices must be able to block high voltage so that current does not flow in the off state, have no power consumption in the on state, and have a small resistance so that high current can flow. For high efficiency, power loss must be minimized and resistance must be reduced during the turn-on state. To increase the breakdown voltage, the thickness and resistivity of the N-drift region must be increased. However, owing to the trade-off relationship, as the breakdown voltage increases, the on-resistance also increases. The super junction structure was proposed to improve this trade-off relationship. In this study, a process simulation using TCAD tool was carried out. Similar to the multi-epitaxial process, the P-pillar was divided into several layers, and the value of each concentration was specified. Thus, the charge balance of the pillar regions was achieved. For the maximum breakdown voltage characteristics and minimum on-resistance characteristics of the deep-trench super junction MOSFET, an experiment was conducted to optimize the cell pitch and pillar of the super junction MOSFET using a five-deep trench.

Influence of the Semiconductor Devices Cooling Conditions on Characteristics of Selected DC–DC Converters

The problem of an influence of cooling conditions of power semiconductor devices on properties of selected DC–DC converters is considered. The new version of electrothermal average model of a diode-transistor switch for SPICE (Simulation Program with Integrated Circuit Emphasis) is used in the investigations. This model makes it possible to take into account thermal inertia of semiconductor devices as well as mutual thermal interactions between these devices. The investigations are performed for boost and buck converters containing the power MOS (Metal-Oxide-Semiconductor) transistor and the diode. Computational results obtained using the proposed model are shown and discussed. Particularly, an influence of thermal phenomena in the diode and the power MOS transistor on the converters output voltage and internal temperature of the semiconductor devices is considered. The correctness of the selected results of computations was verified experimentally.