Power Metal Oxide Semiconductor Field Effect Research Articles

Synergistic effect of total ionizing dose on single-event gate rupture in SiC power MOSFETs

The synergistic effect of total ionizing dose (TID) and single event gate rupture (SEGR) in SiC power metal–oxide–semiconductor field effect transistors (MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.

Single-Event Gate Rupture Hardened Structure for High-Voltage Super-Junction Power MOSFETs

This article presents design for a 650-V super-junction (SJ) power metal–oxide–semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10.

Effect of Gate-Oxide Degradation on Electrical Parameters of Power MOSFETs

Gate oxide in power metal–oxide–semiconductor field effect transistors (MOSFETs) degrades over time. The degradation leads to an accumulation of oxide-trapped charges within the gate oxide and an accumulation of interface-trapped charges at the oxide–semiconductor surface of power MOSFETs. Overtime, such charges significantly alter the electrical parameters of power MOSFETs; to observe this, the electrical parameters are utilized as precursors of gate-oxide degradation. The purpose of this paper is threefold: 1) to propose a new online precursor of gate-oxide degradation—the gate plateau time; 2) to demonstrate a simultaneous dip-and-rebound variation pattern of four precursors of gate-oxide degradation: threshold voltage, gate plateau voltage, gate plateau time, and on-resistance; and 3) to compare the shift tendencies of each precursor over the course of gate-oxide degradation. The existing studies of gate-oxide degradation mechanisms and their effects on threshold voltage and mobility reduction were extended to correlate a variation of all four precursors using analytical expressions. The variation patterns were experimentally verified using high-electric field stressing in two different commercial power MOSFETs. The new precursor, the gate plateau time, was found to be a competitive gate-oxide degradation precursor, as it had a higher positive shift than threshold voltage and gate plateau voltage. In addition, the threshold voltage was found to be the most sensitive indicator of the negative shift (dip), while the on-resistance and gate plateau time were found to be the most sensitive indicators of the positive shift (rebound).

Improvement of radiation response of SiC MOSFETs under high temperature and humidity conditions

The response of hexagonal (4H) silicon carbide (SiC) power metal–oxide–semiconductor field effect transistors (MOSFETs) to gamma-ray irradiation was investigated under elevated temperature and humid conditions. The shift in drain current–gate voltage (ID–VG) curves towards negative voltages and the leakage of ID with a current hump due to elevated temperature irradiation were suppressed under high humidity conditions relative to dry conditions. This result can be explained in terms of the reduction in trapped oxide charge and oxide–SiC interface traps generated by irradiation due to the humid conditions. In addition, during irradiation at elevated temperature in humid conditions, electron traps at the oxide–SiC interface obviously decrease at doses above 100 kGy.

Radiation response of silicon carbide metal–oxide–semiconductor transistors in high dose region

Radiation response of vertical structure hexagonal (4H) silicon carbide (SiC) power metal–oxide–semiconductor field effect transistors (MOSFETs) was investigated up to 5.8 MGy. The drain current–gate voltage curves for the MOSFETs shifted from positive to negative voltages due to irradiation. However, the drain current–gate voltage curve shifts for the MOSFETs irradiated at 150 °C was smaller than those irradiated at room temperature. Thus, the shift of threshold voltage due to irradiation was suppressed by irradiation at 150 °C. No significant change or slight decrease in subthreshold voltage swing for the MOSFETs irradiated at 150 °C was observed. The value of channel mobility increased due to irradiation, and the increase was enhanced by irradiation at 150 °C comparing to irradiation at RT.

Analysis and implementation of a zero‐voltage switching asymmetric pulse‐width modulation converter for high load current application

A soft-switching converter using low voltage and low current stresses of power components is presented for high input voltage and high output current applications. Two input capacitors and four power metal-oxide semiconductor field effect transistors (MOSFETs) are adopted at high voltage side in order to reduce the voltage stress of power switches. Thus, the voltage stress of MOSFETs is clamped at V in /2. Two flying capacitors are adopted at the AC side of two half-bridge converter legs to balance the two input capacitor voltages. Three centre-tapped rectifiers are used at low voltage side in order to share load current and reduce the size of magnetic core and current stress of passive components. Asymmetric pulse-width modulation is used to generate the gate signals of power MOSFETs and regulate output voltage. Based on the resonant behaviour at the transition interval, all power switches can be turned on under zero voltage switching. Finally, experiments are provided to verify the effectiveness of the proposed converter.

Analysis study of sensitive volume and triggering criteria of single‐event burnout in super‐junction metal‐oxide semiconductor field‐effect transistors

Power metal-oxide semiconductor field effect transistors (MOSFETs) are more and more used in atmospheric and space applications. Thus, it is essential to study the influence of the natural radiation environment on the electrical behaviour of vertical double-diffused metal-oxide semiconductor (VDMOS) and super-junction (SJ) MOSFETs. Two-dimensional numerical simulations are performed to define the sensitive volume and triggering criteria of single-event burnout (SEB) for VDMOS and SJ MOSFETs for different configurations of ionising tracks. The analysis of the results allows a better understanding of the SEB mechanism in each structure and allows the behaviour and robustness comparison for these two technologies under heavy-ion irradiation.

Single-Event Burnout Hardening of Power UMOSFETs With Optimized Structure

This paper gives and explains the simulation results of single-event burnout (SEB) hardening in a power metal-oxide semiconductor field-effect transistor U-Shape Metal Oxide Semiconductor Field Effect Transistor (trench-gate MOSFET). It includes p+ plug enlargement and adds a buffer layer that is between the epitaxial layer and substrate. These two hardening solutions are compared and the optimized structure that can prevent SEB is given. The single event gate-rupture (SEGR) threshold voltages in different linear energy transfers are also compared with SEB results. In addition, the simulation results show that the change of gate bias can influence the occurrence of SEGR, and the natural radiation environment at cryogenic temperatures is also considered.

Parasitic Bipolar Effect of a Thin-Film Silicon-on-Insulator Power Metal–Oxide–Semiconductor Field-Effect Transistor at High Temperatures

In this paper, we describe the parasitic bipolar effect of the fabricated thin-film silicon-on-insulator (SOI) power metal–oxide–semiconductor field-effect transistor (MOSFET) at high temperatures. This effect in the on-state was suppressed as temperature increased. This effect in the off-state was promoted as temperature and body contact pitch increased. The parasitic bipolar effect caused by the thermally generated current is enhanced by increasing temperature and decreasing channel length. This reduced breakdown voltage.

A Study on the Design of a Pulse-Width Modulation DC/DC Power Converter

DC/DC Switching power converters are commonly used to generate regulated DC output voltages with high-power efficiencies from different DC input sources. A switching converter utilizes one or more energy storage elements such as capacitors, or transformers to efficiently transfer energy from the input to the output at periodic intervals. The fundamental boost converter studied here consists of a power metal-oxide semiconductor field effect transistor switch, an inductor, a capacitor, a diode, and a pulse-width modulation circuit with oscillator, amplifier, and comparator. A buck converter containing a switched-mode power supply is also studied. In this paper, the electrical characteristics of DC/DC power converters are simulated by simulation program with integrated circuit emphasis (SPICE). Furthermore, power efficiency was analyzed based on the specifications of each component.

4H-SiC Power Metal–Oxide–Semiconductor Field Effect Transistors and Schottky Barrier Diodes of 1.7 kV Rating

4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) and Schottky barrier diodes (SBDs) of 10 A/1.7 kV rating were fabricated and characterized. Suitable design of a drift layer and a junction termination realized stable avalanche breakdown of 1.8 kV. Relatively low on-resistances of 8.3 mΩ cm2 for the MOSFET and 2.2 mΩ cm2 for the SBD were successfully recorded. Temperature dependence of the static characteristics of the SBD showed positive temperature coefficient in both the avalanche breakdown voltage and the differential on-resistance. The MOSFET and SBD were assembled into an SiC module. Its dynamic characterization revealed that the switching loss reduction in the SiC module was as much as 86% in comparison with that of the conventional Si counterpart under a moderate switching condition.

Comparisons of the Hot Carrier Effect in Quasi-Silicon-on-Insulator and Conventional Silicon-on-Insulator Power Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated by Reversed Silicon Wafer Direct Bonding

The hot carrier effect in quasi-silicon-on-insulator (SOI) and conventional SOI power metal–oxide–semiconductor field-effect transistors (MOSFETs) was compared on the basis of experimental results. Device degradation caused by the hot carrier effect in the quasi-SOI power MOSFETs proved to be smaller than in the conventional SOI power MOSFETs because the former can suppress the activation of parasitic bipolar transistors.

Trench Termination Design and Analysis in Low-Voltage N-Channel Trench Power Metal–Oxide–Semiconductor Field-Effect Transistor

In this study, a novel termination is designed in a low-voltage N-channel trench power metal–oxide–semiconductor field-effect transistor (MOSFET) to simplify the fabricating process. In a conventional trench power-MOSFET (PowerMOS), a field oxide with a metal field plate is often used for edge termination. The field oxide only exists in the termination region of the trench PowerMOS; therefore if the termination can be designed without the field oxide, field oxidation can be removed from the fabrication. Trench termination is proposed in this work to replace field oxide termination. The use of multiple trench rings leads to the desired breakdown voltage. The temperature effect in trench termination must be considered owing to the negative coefficient of the threshold voltage (VTH) of the P-type MOS (PMOS) and the temperature. This work also provides a design guideline for trench termination in the low-voltage trench PowerMOS.

Design Considerations for Linear Amplification and Low-Insertion Loss Thin-Film Silicon-on-Insulator Power Metal–Oxide–Semiconductor Field-Effect Transistors

This paper investigate for designing thin-film silicon-on-insulator (SOI) power metal–oxide–semiconductor field-effect transistors (MOSFETs) for linear-amplification and single pole double throw (SPDT)-switch applications. Considering 3.3-V operation (with a lithium ion battery as a power source), channel length of 0.5 µm is the best choice. For linear amplification, it is preferable to suppress the parasitic bipolar effect and reduce the on-resistance. For an SPDT switch, it is preferable to reduce on-resistance and use high-resistivity Si substrate. The effect of the silicon substrate resistivity in radio frequency SOI power MOSFET is found in insertion loss of the SPDT switch.

Numerical Thermal Simulation of Cryogenic Power Modules Under Liquid Nitrogen Cooling

Understanding the thermal performance of power modules under liquid nitrogen cooling is important for the design of cryogenic power electronic systems. When the power device is conducting electrical current, heat is generated due to Joule heating. The heat needs to be efficiently dissipated to the ambient in order to keep the temperature of the device within the allowable range; on the other hand, it would be advantageous to boost the current levels in the power devices to the highest possible level. Projecting the junction temperature of the power module during cryogenic operation is a crucial step in designing the system. In this paper, we present the thermal simulations of two different types of power metal-oxide semiconductor field effect transistor modules used to build a cryogenic inverter under liquid nitrogen pool cooling and discussed their implications on the design of the system.

Characterizing Trench-Gate Power Metal–Oxide–Semiconductor Field Effect Transistor with Multi-Layer Dielectrics at the Trench Bottom

Power devices with a high switching speed and a low conduction resistance are crucially important in power conversion circuits. In this study, a trench-gate power metal–oxide–semiconductor field effect transistor (MOSFET) with a high-density cell design 20.6 Mcell/cm2 was implemented for the first time using multilayer dielectrics with an oxide–nitride–oxide (ONO) structure at the bottom of the trench. The thick ONO dielectric layers at the bottom of the trench compensate for the increase in Miller capacitance per unit area as the cell density increases. The resulting device exhibits excellent characteristics of gate charge, switching power loss, gate oxide quality and practical process stability, superior to those of the conventional structure. An n-channel 25.8 V trench gate MOSFET with a specific on-resistance of 0.15 mΩm2, and RON×QGD figure-of-merit 41 mΩ·nC is presented.

Impact of Silicon-on-Insulator Substrate Parameters on the Radio Frequency Performance of Quasi-Silicon-on-Insulator Power Metal-Oxide-Semiconductor Field Effect Transistors

We have investigated the impact of silicon-on-insulator (SOI) substrate parameters on the radio-frequency performance of quasi-SOI power metal–oxide–semiconductor field effect transistors (MOSFETs) to optimize the device structure. We found that increasing the top silicon layer thickness of the quasi-SOI power MOSFET increased the breakdown voltage and decreased the on-resistance. Increasing the thickness of the top Si layer also increased the cutoff frequency, the maximum oscillation frequency, and the power-added efficiency. The power-added efficiency of a quasi-SOI power MOSFET with a thick buried oxide layer was also higher than that of one with a thinner layer because the thicker buried oxide resulted in lower source-to-drain capacitance, which enables better second-harmonic tuning.

Device Temperature and Heat Generation in Power Metal-Oxide Semiconductor Field Effect Transistors

A numerical thermal-electrical model has been established for a typical power metal-oxide semiconductor field effect transistor (MOSFET) device in this work. The temperature and heat-generation distributions within the device are obtained and their effects on the device I- V characteristics are examined. Drain currents in both the cutoff state and the on-state increase with an increase of ambient temperatures in the entire range of v ds from the ohmic region to the breakdown region. The thermal impact on the I d - V ds curves in the cutoff state and the on-state is displayed in terms of different prebreakdown behaviors. An abrupt temperature rise occurring before the traditionally known onset of the avalanche breakdown of the drain-body p-n junction is observed in this work. Unlike the well-recognized avalanche breakdown mechanism, the microscopic mechanism for this temperature rise is not yet clearly understood. It is observed that, although the highest temperature does not occur in the channel region, the temperature gradient along the channel is the highest in the device domain. It is shown that the maximum heat generation occurs in the channel region. The magnitude of the heat generation in the channel region is found to be two orders higher than that in the drift region. This high local heat generation must be considered in the optimal design of power MOSFET devices to reduce the temperature, and more importantly, the temperature variation in the channel region for a more reliable performance of MOSFET in high-temperature applications.

Effect of ion energy upon dielectric breakdown of the capacitor response in vertical power MOSFETs

The effect of ion energy upon the ion-induced dielectric breakdown response of the capacitor response in vertical power metal-oxide semiconductor field effect transistors (MOSFETs) was investigated. The single event gate rupture response was experimentally determined using mono-energetic ion beams of copper, niobium, and gold. Irradiations were conducted using an ion species tuned to different energies, producing a range of linear energy transfer (LET) values for that ion. Numerous MOSFETs were characterized to identify the onset of ion-induced dielectric breakdown. These data along with previously taken data demonstrated that the ion-induced dielectric breakdown cannot be adequately described in terms of LET, but is better described in terms of atomic number (Z). Based upon these observations, a new semi-empirical expression is presented describing the critical ion-induced breakdown response in terms of Z instead of LET. This expression is shown to be a better single event gate rupture model of the capacitor response.

Effect of Buried Oxide Thickness in a Thin-Film Silicon on Insulator Power Metal-Oxide-Semiconductor Field-Effect Transistor

Effect of buried oxide thickness in a thin-film silicon on insulator (SOI) power metal-oxide-semiconductor field-effect (MOSFET) transistor is demonstrated. In the thin-film SOI power MOSFETs fabricated on a separation by implanted oxygen (SIMOX) substrate, devices with a thin buried oxide showed higher performance than ones with a thick buried oxide. The device with thinner top silicon layer operated in a fully depleted mode. The minimum specific on-resistance of the fabricated device was 66 m Ω· mm2 at a breakdown voltage of 32 V.