Single-Event Burnout Hardening of Power UMOSFETs With Optimized Structure

Abstract

This paper gives and explains the simulation results of single-event burnout (SEB) hardening in a power metal-oxide semiconductor field-effect transistor U-Shape Metal Oxide Semiconductor Field Effect Transistor (trench-gate MOSFET). It includes p+ plug enlargement and adds a buffer layer that is between the epitaxial layer and substrate. These two hardening solutions are compared and the optimized structure that can prevent SEB is given. The single event gate-rupture (SEGR) threshold voltages in different linear energy transfers are also compared with SEB results. In addition, the simulation results show that the change of gate bias can influence the occurrence of SEGR, and the natural radiation environment at cryogenic temperatures is also considered.