Power Metal Oxide Semiconductor Field Effect Transistor Research Articles

On performance evaluation of high‐power, high‐bandwidth current measurement technologies for SiC switching devices

AbstractSilicon carbide (SiC) power metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) switch at an unprecedented speed, even at high currents. For accurate dynamic characterization, current sensors must measure high currents at a high bandwidth. Moreover, at high switching speeds, parasitic impedances in the commutation loop become critical. To ensure high‐accuracy measurements, the current sensor insertion impedance must be minimal. Here, a two‐step current sensor evaluation method is proposed. This method serves the characterization and suitability assessment of high‐power, high‐bandwidth current sensors for fast‐switching applications using SiC power MOSFETs. Conducting a small‐ and a large‐signal transmission behaviour analysis separately results in holistic information about the current sensor behaviour in both time and frequency domain. The proposed method is validated using four commercially available current sensors that are widely used for SiC power MOSFET characterization. The work concludes transferring the knowledge derived in the conducted experiments to a practical, application‐oriented sensor selection guide.

A Brief Review of Single-Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide Power MOSFETs

Radiation hardening of power MOSFETs (metal oxide semiconductor field effect transistors) is of the highest priority for sustaining high-power systems in the space radiation environment. Silicon carbide (SiC)-based power electronics are being investigated as a strong alternative for high power spaceborne power electronic systems. SiC MOSFETs have been shown to be most prone to single-event burnout (SEB) from space radiation. The current knowledge of SiC MOSFET device degradation and failure mechanisms are reviewed in this paper. Additionally, the viability of radiation tolerant SiC MOSFET designs and the modeling methods of SEB phenomena are evaluated. A merit system is proposed to consider the performance of radiation tolerance and nominal electrical performance. Criteria needed for high-fidelity SEB simulations are also reviewed. This paper stands as a necessary analytical review to intercede the development of radiation-hardened power devices for space and extreme environment applications.

4H-SiC/SiO2 Interface Degradation in 1.2 kV 4H-SiC MOSFETs due to Power Cycling Tests

Power cycling tests (PCTs) assess the reliability of power devices by closely simulating their operating conditions. A PCT was performed on commercially available 1.2 kV 4H-SiC power metal–oxide–semiconductor field-effect transistors to observe its impact on the 4H-SiC/SiO2 interface. High-resolution transmission electron microscopy and electron energy loss spectroscopy measurements showed variations in the length of the 4H-SiC/SiO2 transition layer, depending on whether the device was power cycled. Moreover, the total resistance at Vg >> Vt in Rtot − (Vg-Vt)−1 graph increased to 16.5%, while it changed more radically to 47.3% at Vg ≈ Vt. The threshold voltage shifted negatively. These variations cannot be expected solely through the wearout of the package.

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

Establishment of analytical model for electrostatic discharge gate-to-source capacitance of power metal-oxide-semiconductor field-effect transistor

In the actual human body model (HBM) test, it is found that the electrostatic discharge (ESD) test results of various power metal-oxide-semiconductor field-effect transistor (MOSFET) devices show asymmetry between forward withstand voltage and reverse withstand voltage, while the ESD process does not distinguish between positive direction and negative direction. Large differences between forward and reverse withstand voltages are unacceptable for power MOSFETs or as ESD protection devices. The problem of its causing device failure is particularly pronounced. In this work, by establishing the analytical model of gate-to-source capacitance of SGT-MOSFET, VUMOSFET and VDMOS under the forward and reverse voltages, we comparatively analyze the reasons for the asymmetry of the forward and reverse withstand voltages and their different ratios of the three kinds of power MOSFETs, which provides a theoretical basis for testing the device’s ESD and the analyzing their reliability. It is found that the ESD forward and reverse withstand voltage asymmetry phenomena of different power MOSFET structures are related to the variation of gate-to-source capacitance, caused by the reverse-type layer. When a forward voltage is applied across the gate and source, the device gate-to-source capacitance consists of the oxide layer capacitance around the gate in parallel; when a reverse voltage is applied, the gate-to-source capacitance consists of the virtual gate-to-drain capacitance in series with the inverse layer capacitance and then in parallel with the other oxide layer capacitance around the gate. This results in a decrease of the gate-to-source capacitance at the reverse voltage, making the device reverse withstand voltage greater than the forward withstand voltage. The difference in the ratio of ESD reverse withstand voltage to forward withstand voltage among different devices is related to the change of the capacitance of the inverse layer in the gate-to-source capacitor under reverse voltage caused by the difference in device structure.

Dynamic Dead-Time Compensation Method Based on Switching Characteristics of the MOSFET for PMSM Drive System

In order to effectively avoid the shoot-through issue of the semiconductor device (such as the power metal-oxide-semiconductor field-effect transistor (MOSFET)) adopted in the phase leg of the motor drives, a dead-time zone should be inserted. However, the nonlinearity caused by the dead-time effect will bring about voltage/current distortion, as well as high-order harmonics, which largely degrades the performance of motor drives, especially in low-speed operations with slight loads. In this paper, a dead-time compensation method is proposed to suppress such side effects caused by dead-time zones and improve the performance of motor drives. Compared with other existing methods, the proposed method is mainly focused on the switching characteristics of the power MOSFET, which is directly relative to the compensation time in each pulse-width modulation (PWM) period. Firstly, a detailed derivation process is elaborated to reveal the relationship between compensation time and the switching performance of the MOSFET. Meanwhile, the switching process of the MOSFET is also well analyzed, which summarizes the variations in the switching time of the MOSFET with a varied load current. Then, the multipulse test (MPT) is carried out to obtain accurate values of the switching time with the varied load current in a wide range (0–80 A) and form a 2D lookup table. As a result, the compensation method can easily be realized by combining the lookup table and linear interpolation based on the phase current of the motor dynamically. Finally, the effectiveness of the proposed method is verified based on a 12 V permanent magnet synchronous machine (PMSM) drive system. According to the relative experiment results, it can be clearly observed that the time-domain waveform distortion, high-order harmonics, and total harmonic distortion (THD) value are reduced significantly with the proposed dynamic compensation method.

Simple Hybrid Model for Estimating Remaining Useful Life of SiC MOSFETs in Power Cycling Experiments

Recording and prediction of the accumulated damage, which will eventually lead to the failure of power electronic modules, is an aspect of high importance for power electronic systems design and, in particular, for development of Prognostic and Health Management (PHM) schemes for in-field applications. To this end, this paper presents a simple and cost-effective prognostic method for predicting the remaining useful life (RUL) of TO-247 packaged silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) subjected to power cycling experiments. The model assumes that the major failure mode is bond-wire lift-off and uses a damage accumulation scheme based on Paris’ crack law. The only inputs to the model are historical data on the average junction temperature swing and the temperature-compensated drain-source ON-state resistance at the peak temperature of the current cycle. Using only these two input values, the model is shown to predict RUL with surprising accuracy for the range of constant current loads determining cycling conditions under which the test data series have been acquired. This work is a first step in an ongoing project towards building more elaborate prognostic schemes for RUL-determination of SiC power MOSFETs in actual working conditions, using physics-informed neural networks (PINNs).

Charge pumping electrically detected magnetic resonance of silicon carbide power transistors

Silicon carbide (SiC) power devices are becoming central components in high voltage electronics. However, defects at interfaces and in the bulk continue to severely impact their reliability and performance. Here, we develop a charge pumping method to characterize SiC/SiO2 interface defects in fully fabricated commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The method is then used to address spin states at the SiC/SiO2 interface via charge pumping electrically detected magnetic resonance (CP-EDMR). We apply these methods to investigate the power MOSFET after electron irradiation over a dose range of 1013−1017 cm−2. We finally discuss CP-EDMR as a technique to interrogate spins during device operation for real-time monitoring of the device quality, performance, and degradation and as a probe for local magnetic fields.

Review on the Reliability Mechanisms of SiC Power MOSFETs: A Comparison Between Planar-Gate and Trench-Gate Structures

To clarify the current research situation and offer a better understanding of the reliability for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs), a comparison among the reliability mechanisms between planar-gate and trench-gate SiC power MOSFETs, which have not been comprehensively summarized, is made in this work. The latest studies focusing on the reliability issues of commercial SiC MOSFET products, including the planar-gate device, the double-trench device and the asymmetric trench-gate device, are reviewed. For the existing of the gate trenches and the unique structures protecting them, SiC trench-gate MOSFETs express quite different instability phenomena from the planar-gate ones under various ultimate and long-term electro-thermal stresses. The influences of these stresses closely related to the practical operation conditions on SiC power MOSFETs, including the avalanche stress, the short-circuit (SC) stress, the surge current stress of the body diode, and the switching stress, are discussed and reviewed in details.

On the Frequency Dependence of the Gate Switching Instability in Silicon Carbide MOSFETs

Silicon carbide power metal-oxide semiconductor field-effect transistors (MOSFETs) are suitable for more compact and energy efficient electric power conversion, pushing forward numerous key technologies in emission-free mobility and green power generation. These applications require fast gate switching up to hundreds of kilohertz. Typically, to assure a clear turn-off state of the electron channel, a negative turn-off gate bias is used in conjunction with a positive turn-on gate bias. Recently, several reports have revealed a new and so far unknown degradation mechanism that emerges during such operation conditions in apparently all commercial silicon carbide MOSFETs. As this mechanism arises upon gate switching, the terms gate switching instability (GSI) and gate switching stress (GSS) for the mechanism and the associated stress, respectively, have been introduced.Here, we show that this degradation mechanism does not depend on the used frequency up to at least 2 MHz, but that it is actually related to the cumulative number of switching cycles. For this purpose, we performed measurements at various frequencies comprising ultra-fast in-situ measurements of the threshold voltage and pre- and post-stress characterization by impedance analysis. The results are important both for understanding the underlying physics and for developing a correct methodology for industrial device qualification.

650V Vertical SiC MOSFETs and Diodes with Improved Terrestrial-Neutron Single-Event Burnout

Silicon carbide (SiC) power devices such as Schottky diodes and metal-oxide semiconductor field-effect transistors (MOSFETs) are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state. In this study the effects of the drift layer design of 650V SiC vertical power diodes and MOSFETs have been studied. TCAD simulations of different device designs have been performed, and fabricated device single-event burnout (SEB) properties are compared between the devices fabricated. We find that the standard 650V devices have a low area-scaled failure-in-time (FIT/cm2) such that essentially no failures (0.01 FIT/cm2) are expected at 400V drain-source bias (VDS) operation and below. An improved design allows the SEB failure rate curve to be shifted downward in failure rate, such that at for a given VDS operation condition, the FIT/cm2 can be decreased by 10 - 100 times, depending on the VDS value. This allows operation at about 75V higher VDS value with a similar SEB failure rate, allowing these devices to be used in a wider range of applications.

Comparison of the Performance-Degrading Near-Interface Traps in Commercial SiC MOSFETs

This paper presents a comparison of the density of performance-degrading near-interface traps (NITs) in the most commonly available 1200 V commercial N-channel SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). A recently developed integrated-charge technique was used to measure the density of NITs with energy levels aligned to the conduction band, which degrade MOSFET’s performance by capturing and releasing electrons from the channel biased in the strong-inversion condition. Trench MOSFETs of one manufacturer have lower densities of these NITs in comparison to MOSFETs with the planar gate structure, corresponding to observed higher channel-carrier mobility in trench MOSFETs. Different response-time distributions were also observed, corresponding to different spatial location of the measured NITs.

Synergistic effect of total ionizing dose on single-event gate rupture in SiC power MOSFETs

The synergistic effect of total ionizing dose (TID) and single event gate rupture (SEGR) in SiC power metal–oxide–semiconductor field effect transistors (MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.

Electrically Active Defects in SiC Power MOSFETs

The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect.

An ultralow specific on-resistance bidirectional trench power MOSFET with RESURF stepped oxide

This paper presents an ultralow specific on-resistance (Ron,sp) bidirectional trench power metal-oxide-semiconductor field effect transistor (MOSFET) with RESURF stepped oxide (RSO) for lithium-ion (Li-ion) battery protection circuit application. Compared with the conventional dual die bidirectional switches, the proposed single die structure almost halves the total die area with the same cell pitch. Moreover, the drift region under reverse blocking condition is a 2-D depletion and due to the RSO-assisted depletion effect, the concentration of the drift region under reverse blocking condition can be approximately increased by one order, thus a smaller on-state resistance is obtained. Besides, the parasitic transistor is well suppressed due to the cathode short structure for forwardly and a breakdown margin for reversely blocking conditions, respectively. Consequently, based on the analytical design and simulation, the novel single die bidirectional switch ultimately achieves an ultralow Ron,sp of 1.84 mΩ⋅mm2 with a bidirectional breakdown voltage (VB) of 20 V, which has a better figure of merit (FOM).

A core drain current model for β-Ga2O3 power MOSFETs based on surface potential

For the first time, a core drain current model based on surface potential without any implicit functions is developed for beta-phase gallium oxide (β-Ga2O3) power metal-oxide-semiconductor field-effect transistors (MOSFETs). The surface potential solution is analytically deduced by solving the Poisson equation with appropriate simplification assumptions in accumulation, partial-depletion, and full-depletion modes. Then, the drain current expression is analytically derived from the Pao–Sah integral as a function of the mobile charge density obtained from the surface potential at the source and drain terminals. In addition, nonlinear resistors in the source/drain access region are considered. It continuously predicts the characteristics of β-Ga2O3 power MOSFETs in all operation modes, including accumulation mode, partial-depletion mode, and full-depletion mode. Furthermore, the validity of the model is verified by comparing the results of the model with the numerical simulations carried out with the technology computer-aided design (TCAD) tool ATLAS Device Simulator from Silvaco. Good agreement between the proposed model and TCAD simulations is shown for β-Ga2O3 power MOSFETs with different intrinsic channel lengths, channel doping concentrations, and channel thicknesses. Ultimately, the Gummel symmetry test and the harmonic balance simulation test are performed to validate the model’s robustness and convergence.

Analysis of Ruggedness of 4H-SiC Power MOSFETs with Various Doping Parameters

This work investigates the effect of the doping concentration of SiC power metal-oxide–semiconductor field-effect transistors (MOSFETs) under an unclamped inductive switching (UIS) condition. Switching circuits such as inverters and motor-drive circuits often face unexpected operating conditions; therefore, a UIS test is performed to assess the avalanche ruggedness of the device, and design parameters such as the doping concentration should be considered to improve the UIS characteristics. Technology computer-aided design circuit simulation results, such as the current flows during failure and electrical changes, were obtained by changing the doping concentration of each region in the SiC power MOSFET.

A 100‐V trench power MOSFET with taper‐shielded gate and non‐uniform drift region doping profile

AbstractA 100‐V Taper‐Shielded trench Gate (TSG) power metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with superior figure‐of‐merit (FOM) is proposed and investigated in this paper. The gate of the proposed TSG‐MOSFET has a tapered shape to reduce the gate‐to‐drain overlap capacitance (CGD) and the gate charge (QG). The vertical drift region doping profile of the proposed TSG‐MOSFET is enhanced in two ways. First is to use a multi‐step epitaxial growth to produce a non‐uniform doping profile. Second is to place a lightly doped n‐region at the trench bottom. The bulk electric field in the blocking state can be more evenly distributed, allowing a shorter drift region and lower specific ON‐resistance (RON,sp). Both technology computer‐aided design (TCAD) simulations and experiments were performed to evaluate the proposed device. The proposed device exhibits an improved RON,sp of 27 mΩ·mm2 with a breakdown voltage (BV) of 105 V. The third quadrant performance and the reverse recovery characteristics are also greatly improved. During reverse conduction, the amount of the excessive carriers stored in the drift region is reduced due to the shortened drift region and optimized drift region doping profile. The reverse recovery charge (Qrr) is decreased from 70 to 49 nC. When compared to its state‐of‐the‐art counterparts, the measured [RON × QG] FOM and the Qrr showed a reduction of 23% and 28%, respectively.

Degradation Behavior and Mechanism of SiC Power MOSFETs Under Repetitive Transmission Line Pulse Stress

The electrostatic discharge robustness of silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) are investigated by the transmission line pulse (TLP) method. The degradation behavior of key electrical parameters of the device under repetitive TLP stress is investigated. A decrease in threshold voltage, an increase in gate leakage current, and the degradation of gate capacitance parameters are observed compared with the prestress values. Low-frequency noise (LFN) test results show that after multiple TLP stress cycles, the typical leakage current noise of the device increases by approximately one order of magnitude compared to prestress, which means that the trap density extracted based on the McWhorter model increases by one order of magnitude after 1000 TLP stress pulses. Furthermore, sources of defects in the gate oxide dielectric of the devices after stresses are analyzed. The physical mechanism of the changes of SiC MOSFETs characteristics could be attributed to the hole trapping by oxygen vacancy defects and single carbon interstitial in the oxide layer after TLP stresses, which induces an electrostatic effect and results in the changes in the electrical properties of the devices. The results may be useful in the design and application of SiC power MOSFETs.

Influence of SiC reinforcement on microstructural and thermal properties of SAC0307 solder joints

The effect of SiC nano-phases (nano-particles and nano-fibers) addition into SAC0307 solder paste was investigated on the thermal and microstructural properties of the composite solder joints. The nano-phases were used between 0.125 and 1 wt%, and they were mixed into the solder paste by ball milling process. For the study power MOSFET (metal oxide semiconductor field effect transistor) components were soldered onto metal core printed circuit boards (MCPCBs). The thermal impedance Zth(t) and thermal resistance Rth of MOSFETs were measured by an indirect electrical method. Furthermore, the void formation and the microstructure of solder joints were also studied. The solderability and voiding properties of the composite solder alloys were acceptable. It was found that in 0.5 wt% amount, SiC nano-particles have positive effects on the thermal parameters of the solder joints, which could be explained by the IMC (intermetallic compound) layer growth suppression effect of the nano-phases. The microstructural analysis revealed that the microstructural refinement of the composite solder joints differs in the case of nano-particles and nano-fibers.