Power Metal Oxide Semiconductor Field Effect Transistor Research Articles

Updated structure of vertical double-diffused MOSFETs for irradiation hardening against single events

The gate oxide layer and parasitic bipolar junction transistor are inherent elements of vertical double-diffused power metal–oxide–semiconductor field-effect transistors (MOSFETs). Single-event gate rupture (SEGR) and single-event burnout (SEB) may be triggered by penetration of energetic ions through sensitive regions of such MOSFET devices when used in space environments. Based on the recombination mechanism in a heavily doped P+ buried layer and the higher breakdown voltage when using a thick oxide layer, a new structure for power MOSFETs that are irradiation hardened against SEGR and SEB was developed in this work, based on three typical characteristics: an N+ buried layer, a P+ buried layer, and a thick oxide above the neck. The results reveal that the safe operation region of such an N-channel power MOSFET in a single-event irradiation environment is enhanced by 300 % for a linear energy transfer value of 98 MeV cm2/mg. Such structures could be widely used when designing single-event irradiation-hardened power MOSFETs.

Combination of thermal cycling and vibration loading effects on the fatigue life of solder joints in a power module

In this work, the combination of vibration loading and thermal cycle effects on the fatigue properties of a solder joint in a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) discrete was investigated. The fatigue mechanism under each loading mode was individually analyzed, and then according to the incremental damage superposition approach, the simultaneous effects were thoroughly studied. Under thermal cycling, the creep behavior of the solder is linked to the fatigue life. In fact, the creep accumulated strain in each thermal cycle has a straight relation to the failure time of solder joint. The origin of stress/strain in the assembly is owing to the sharp difference between coefficients of thermal expansions of the components in the electronic package. Regarding the vibration loading, the root mean square of peeling stress as a widely acceptable failure indicator was used to evaluate the vibration effects on the fatigue life. It is determined that the maximum stress is concentrated at the corner of solder layer. This result was similar to the outcomes of thermal cycling. The results also indicated that the combination of thermal and mechanical loadings accelerates the failure of the solder joint of the power MOSFET. Furthermore, the experimental and simulation studies showed similar results and approved the crack initiation at the corner of solder layer.

Incorporation of hafnium and platinum metal in vertical power MOSFETs

A novel, vertical single-diffused metal–oxide–semiconductor (VSDMOS) structure is proposed by applying workfunction engineering to a vertical power metal–oxide–semiconductor field-effect transistor (MOSFET) with source and drain regions formed using the charge plasma concept. Electron and hole plasma was induced by employing hafnium and platinum metal. Furthermore, the electrical characteristics of the proposed VSDMOS were compared with those of conventional vertical double-diffused metal–oxide–semiconductor devices, revealing that the proposed VSDMOS exhibits a 14 % increase in current driving capability, with improved breakdown voltage.

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

The trench gate structure is one of the promising techniques to reduce on-state resistance (Ron) for silicon power devices, such as insulated gate bipolar transistors and power metal–oxide–semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the Ron of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

Hybrid full‐bridge converter for DC microgrids: analysis and implementation

This study presents a soft-switching converter for direct current microgrid applications. The studied converter includes n cells of the hybrid full-bridge converter with primary-series–secondary-parallel connection for high-voltage input and large current output applications. Thus, the voltage stress of power switches and the current stress of rectifier diodes are decreased. Therefore, the low-voltage stress and low conduction resistance of power metal–oxide–semiconductor field-effect transistors are utilised in the studied converter to reduce conduction losses on power switches. The flying capacitors are connected between each circuit cell to prevent voltage unbalance on input split capacitors. On each circuit cell, a full-bridge converter with an additional half-bridge circuit is employed to achieve low circulating current losses, less output inductance and a wide range of zero-voltage switching. Finally, the studied converter with 1800 W rated power is constructed and tested to verify the theoretical analysis.

Development of an electronic load I-V curve tracer to investigate the impact of Harmattan aerosol loading on PV module pern2tkformance in southwest Nigeria

This study investigates the impact of the seasonal Harmattan aerosol loading on PV module efficiency at a station in Southwest Nigeria. To this end, a simple, open-source, cost effective electronic load I-V curve tracer was developed to compare the I-V characteristics of a pair of horizontally positioned 80 W monocrystalline modules for the duration of the Harmattan period. The control module was regularly cleaned manually and the other module left to accumulate the Harmattan dust deposits. In order to obtain the modules’ characteristic parameters, an Arduino-based pulse width modulation (pwm) duty cycle was implemented to vary simultaneously, the gate-source voltages, VGS, of two power metal-oxide semiconductor field-effect transistors (MOSFETs) acting as fast variable loads for the modules. Experimental results acquired from the prototype circuit demonstrate that this method provides a more accurate approach and faster response than the resistive load tracer method. The prototype instrument was able to measure and reproduce characteristic curves that are obtainable from the more expensive branded products. Resulting curves depict reduction in the short circuit current, ISC, the current at maximum power, IMP, the power output, PMP and the efficiency, η of the dusty module by more than 18% in comparison with the control module over the measurement period.

Low-power CMOS integrated current sensor for current-mode DC-DC buck converter

PurposeThis paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter.Design/methodology/approachThe integrated DC-DC converter, which is composed of feedback control circuit and power block, is designed with 0.35-µm CMOS process. Current sensor in the control circuit is integrated with sense-FET and voltage-follower circuits to reduce power consumption and improve its sensing accuracy. In the current-sensing circuit, the size ratio of the power metal oxide semiconductor field effect transistor (MOSFET) to the sensing transistor (K) is 1,000, and a current-mirror is used for a voltage follower. N-channel MOS acts as a switching device in the current-sensing circuit, where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time.FindingsExperiment shows that the current sensor is operated with accuracy of more than 85 per cent, and the transient time of the error amplifier is controlled within 100 µs. The sensing current is in the range of a few hundred µA at a frequency of 0.6-2 MHz and an input voltage of 3-5 V. The output voltage is obtained as expected with the ripple ratio within 5 per cent.Originality/valueThe proposed current sensor in DC-DC converter provides an accurately sensed inductor current with a significant reduction in power consumption in the range of 0.2 mW. High-accuracy regulation is obtained using the proposed current sensor. As the sensor utilizes simple switch-type voltage follower and sense-FET, it can be widely applied to other low-power applications such as high-frequency oscillator and over-current protection circuit.

Design considerations for charge‐compensated fast‐switching power MOSFET in the medium‐voltage range

Low-voltage power metal-oxide-semiconductor field-effect transistors (MOSFETs) based on charge compensation using a field plate offer a significant reduction of the area-specific on-resistance. The extension of their blocking capability into the so-called medium-voltage range of 150-300 V promises devices with excellent properties being attractive for a wide range of applications. There are two approaches how this voltage-range extension can be realised. Both concepts are linked to different device performance and different development effort. This study discusses both concepts using the example of the 150 V device class and compares the performance gained at the device and application level.

Improved SiC Power MOSFET Model Considering Nonlinear Junction Capacitances

Silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (mosfet s) have been applied in high-power and high-frequency converters recently. To effectively predict characteristics of SiC power mosfet s in the design phase, a simple and valid model is needed. In this paper, a simple improved SiC power mosfet behavioral model is proposed using SPICE language. Key parameters in the model are analyzed and determined in detail, including parasitic parameters of the power module, steady-state characteristic parameters, and nonlinear parasitic capacitances. The effect of negative turn- off gate drive voltage is considered and a continuously differentiable function is proposed to describe the gate–source capacitance. Experimental validation is performed under a double pulse circuit employing an N -channel power mosfet half-bridge module CAS300M12BM2 (Cree Inc.) rated at 300 A/1200 V. The main switching dynamic characteristic parameters of the model have been compared with those of the measured results. The results show that taking gate–source capacitance as a linear value as most previous models do will cause significant turn- on deviations between experiment and simulation results, while the improved model is more accurate compared with the measured results.

Study the Effects of Photon Radiation on Power MOSFET for Harsh Environment Application

The rapid growth of the advanced technologies in power electronics system gives a challenge to the electronic device to sustain with the modern technologies nowadays. The challenges are also including the place where the system was installed for example the application in the harsh environment. Harsh environment application requires an electronic device deals with radiation pollution. Hence, the electronic device will suffer from this phenomenon and make the whole system to malfunction and break down. Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is one type of electronic device that is the most broadly for high voltage and high switching speed application. The aim of this paper is to studies the photon radiation effect toward the Power MOSFET performance. The study focus on the changing of the electrical characteristics of the device after radiated with photon radiation. Process simulation and Device simulation tools in Sentaurus Synopsys Software used for the research to validate all the theory.

Extraction method of interfacial injected charges for SiC power MOSFETs

An improved novel extraction method which can characterize the injected charges along the gate oxide interface for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. According to the different interface situations of the channel region and the junction FET (JFET) region, the gate capacitance versus gate voltage (Cg-Vg) curve of the device can be divided into three relatively independent parts, through which the locations and the types of the charges injected in to the oxide above the interface can be distinguished. Moreover, the densities of these charges can also be calculated by the amplitudes of the shifts in the Cg-Vg curve. The correctness of this method is proved by TCAD simulations. Moreover, experiments on devices stressed by unclamped-inductive-switching (UIS) stress and negative bias temperature stress (NBTS) are performed to verify the validity of this method.

High voltage gain interleaved DC–DC converter with minimum current ripple

A new interleaved high step-up DC–DC converter is presented in this study which integrates coupled inductors and voltage multipliers techniques into interleaved structure to provide high voltage gain without extreme duty cycle. The voltage stress across power metal–oxide–semiconductor field-effect transistors is very low, so low voltage rating switches with lower R ds(on) can be used. A modified version of winding cross-coupled inductors technique is employed to minimise the input current ripple, and also the reverse recovery problem of the output diodes is alleviated because of the leakage inductance of the coupled inductors. Also, the leakage energy is absorbed and recycled to the output by the passive clamp scheme. In addition, automatic current sharing performance between the interleaved phases is established without any extra circuit. The operating principles of the proposed converter are explained and the theoretical analysis is provided, and in order to verify the effectiveness of the proposed converter, a 170 W, 30–360 V laboratory prototype is implemented.

A SiC Power MOSFET Loss Model Suitable for High-Frequency Applications

The reduced chip size and unipolar current conduction mechanism make silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) suitable for high-frequency power electronics applications. Modeling the switching process of the SiC power MOSFET with parasitic components is important for achieving higher efficiency and power density system design. Therefore, this paper proposes a new concise yet accurate switching loss model for SiC power MOSFETs. Addressing the limitations in experimental measurements, numerical simulations are conducted to validate the proposed model taking the output capacitance C oss discharge and charge into consideration. The role of the parasitic components in the second-order model is discussed in depth for switching losses. Furthermore, this paper also provides guidelines in designing the gate driver for ultrafast SiC power MOSFETs.

(Invited) Three-Section Adjusted Field Limited Rings Applicable for SiC 2200V Power MOSFETs

Due to excellent intrinsic properties of silicon carbide (SiC), SiC power metal oxide semiconductor field effect transistors (MOSFETs) potentially become a desirable candidate featuring high blocking voltage with ultra-low conduction resistance for high efficiency power applications [1]. In order to achieve expected avalanche breakdown in SiC device, junction termination techniques are paramount to alleviate the crowded high electric field at the periphery of active regions [2]. Previous works related with various SiC junction termination techniques mainly focus on junction termination extension (JTE) and related variations, like hybrid, bevel-assist, multiple-shallow-trench, and counter-doped JTE [3-5]. However, little reports on field limited rings (FLRs) technique for SiC power device are released. Actually, the FLR technique features less tight process control and desirable reliability, benefiting SiC-based industrial power applications. In this paper, three section adjusted field limited rings (TS-FLRs) are proposed and fabricated for 2200V rating for motor extraction applied in high-speed trains and hybrid/electric vehicles. The proposal not only avoids tight control of etching depth and ion implantation dose required by aforementioned multiple JTE structures, but also shows a desired process tolerance without complicated designs and extra process step for the TS-FLRs. The schematic cross-section view of the proposed TS-FLRs is fabricated on an 18μm thick drift layer of with doping concentration of 5E15 cm-3 as shown in Fig. 1. The TS-FLRs are implanted with formation of P base region of active region in same process step, followed by an 1800 degree C high temperature activation. Then a thick passivation layer is deposited on the termination region to effectively avoid influences from following processes. The TS-FLRs is designed to three sections characterizing space of FLRs S1 and width of FLRs W1 in section I, S2 and W2 in section II, as well as S3 and W3in section III for substantially reducing design complex of FLRs. Firstly, due to formation at same fabrication step, the total implantation dose is carefully considered for both BV and V th. TS-FLRs have an evidently better stability based on different total doses than that of fixed space and same width ones (F-FLRs) as shown in Fig. 2. Moreover, the TS-FLRs evidently show stable breakdown performances dependent on various spaces while a weak tolerance of space definition of F-FLRs. Furthermore, the influence of TS-FLRs with different widths of ring and with different max energies of implantation on breakdown voltage is evaluated, combining analysis of electric field distribution inside termination region by Sentaurus simulation. After optimized design, TS-FLRs and F-FLRs are fabricated at same process level with SiC power MOSFETs as shown in Fig. 3. Fig. 4 shows that the breakdown voltage of the MOSFETs with TS-FLRs is as high as 2500V, a significant enhancement in comparison with F-FLRs. Acknowledge: The authors thank China Railway Rolling Stock Corporation. Reference: J. W. Palmour, L. Cheng, V. Pala, E. V. Brunt, D. J. Lichtenwalner, G. –Y Wang, J. Richmond, M. O’Loughlin, S.Ryu, S. T. Allen, A. A. Burk and C. Scozzie, “Silicon Carbide Power MOSFETs: Breakthrough Performance from 900V up to 15kV,” 2014 26th Int. Symp. Power Semiconductor Devices ICs (ISPSD)., pp.79-82, Jun. 2014, doi: 10.1109/ISPSD.2014.6855980.T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology: growth, characterization, devices and application. Singapore: Wiley, Nov. 2014.W. Sung, B. J. Baliga and A. Q. Huang, “Area-Efficient Bevel-Edge Termination Techniques for SiC High-Voltage Devices,” IEEE Trans. on Electron Devices., vol. 63, no. 4, 2016, pp. 1630 - 1636, doi: 10.1109/TED.2016.2532602.H. Elahipanah, A. Salemi, C.-M. Zetterling and M. Ostling, “ 5.8-KV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension,” IEEE Electron Device Letters., vol. 36, no. 2, pp. 168 - 170, Feb. 2015, doi: 10.1109/LED.2014.2386317.J. -Y. Jiang, H.-C. Hsu, K.-W. Chu, C.-F. Huang and F. Zhao, “Experimental Study of Counter-Doped Junction Termination Extension for 4H–SiC Power Devices,” IEEE Electron Device Letters., vol. 36, no. 7, pp. 699 - 701, July. 2015, doi: 10.1109/LED.2015.2428617. Figure 1

LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs

This paper presents a method of thermal balancing for monolithic power integrated circuits (ICs). An on-chip temperature monitoring sensor that consists of a poly resistor strip in each of multiple parallel MOSFET banks is developed. A temperature-to-frequency converter (TFC) is proposed to quantize on-chip temperature. A pulse-width-modulation (PWM) methodology is developed to balance the channel temperature based on the quantization. The modulated PWM pulses control the hottest of metal-oxide-semiconductor field-effect transistor (MOSFET) bank to reduce its power dissipation and heat generation. A test chip with eight parallel MOSFET banks is fabricated in TSMC 0.25 μm HV BCD processes, and total area is 900 × 914 μm2. The maximal temperature variation among the eight banks can reduce to 2.8 °C by the proposed thermal balancing system from 9.5 °C with 1.5 W dissipation. As a result, our proposed system improves the lifetime of a power MOSFET by 20%.

Modular resonant DC/DC converter for DC grid system applications

A modular resonant DC/DC converter for DC microgrid system applications is provided in this study. Half-bridge circuit cells are connected in series to reduce the voltage stress on each half-bridge circuit, so that power metal–oxide–semiconductor field-effect transistors with high-frequency operation can be used at high-voltage DC/DC converters and the converter size can be reduced. To balance input split voltages, flying capacitors are used and connected between each half-bridge circuit. Therefore, input split voltages can be balanced automatically in each switching cycle without using the complexity control scheme. Resonant circuit is used in each half-bridge cell to realise the zero-voltage turn-on for power switches and zero current turn-off for rectifier diodes over the wide load range. Therefore, the proposed modular resonant DC/DC converter with high-circuit efficiency can be achieved. The output sides of half-bridge circuit cells are connected in parallel to reduce the current stress of all passive components. Finally, the circuit performance of the proposed converter is evaluated by experiments.

Improvement of reverse blocking performance in vertical power MOSFETs with Schottky–drain-connected semisuperjunctions**Project supported by the National Natural Science Foundation of China (Grant Nos. 61574112, 61334002, 61306017, 61474091, and 61574110) and the Natural Science Basic Research Plan in Shaanxi Province of China (Grant No. 605119425012).

To enhance the reverse blocking capability with low specific on-resistance, a novel vertical metal–oxide–semiconductor field-effect transistor (MOSFET) with a Schottky–drian (SD) and SD-connected semisuperjunctions (SD-D-semi-SJ), named as SD-D-semi-SJ MOSFET is proposed and demonstrated by two-dimensional (2D) numerical simulations. The SD contacted with the n-pillar exhibits the Schottky-contact property, and that with the p-pillar the Ohmic-contact property. Based on these features, the SD-D-semi-SJ MOSFET could obviously overcome the great obstacle of the ineffectivity of the conventional superjunctions (SJ) or semisuperjunctions (semi-SJ) for the reverse applications and achieve a satisfactory trade-off between the reverse breakdown voltage (BV) and the specific on-resistance (). For a given pillar width and n-drift thickness, there exists a proper range of n-drift concentration (N), in which the SD-D-semi-SJ MOSFET could exhibit a better trade-off of –BV compared to the predication of SJ MOSFET in the forward applications. And what is much valuable, in this proper range of N, the desired BV and good trade-off could be achieved only by determining the pillar thickness, with the top assist layer thickness unchanged. Detailed analyses have been carried out to get physical insights into the intrinsic mechanism of –BV improvement in SD-D-semi-SJ MOSFET. These results demonstrate a great potential of SD-D-semi-SJ MOSFET in reverse applications.

Normally-Off C–H Diamond MOSFETs With Partial C–O Channel Achieving 2-kV Breakdown Voltage

Diamond has unique physical properties, which show great promise for applications in the next generation power devices. Hydrogen-terminated (C–H) diamond metal–oxide–semiconductor field-effect transistors (MOSFETs) often have normally-on operation in devices, because the C–H channel features a p-type inversion layer; however, normally-off devices are preferable in power MOSFETs from the viewpoint of fail safety. We fabricated hydrogen-terminated (C–H) diamond MOSFETs using a partially oxidized (partial C–O) channel. The fabricated MOSFETs showed a high breakdown voltage of over 2 kV at room temperature and normally-off characteristics with a gate threshold voltage $\text{V}_{\mathrm{th}}$ of −2.5–−4 V.

GaN-on-Silicon Power Devices: How to Dislodge Silicon-Based Power MOSFETs [Expert View

Gallium nitride (GaN) power transistors designed for efficient power conversion have been in production for seven years. New markets, such as light detection and ranging, envelope tracking, and wireless charging, have emerged due to the superior switching speed of GaN. These markets have enabled GaN products to achieve significant volumes, low production costs, and an enviable reliability reputation. All of this provides adequate incentive for the more conservative design engineers in applications such as dc–dc converters, ac–dc converters, and automotive to start their evaluation process. So what are the remaining barriers to the conversion of the US$12 billion silicon power metal–oxide–semiconductor field-effect transistor (MOSFET) market? In a word: confidence. Design engineers, manufacturing engineers, purchasing managers, and senior management all need to be confident that GaN will provide benefits that more than offset the risk of adopting a new technology. Let’s look at three key risk factors: supply chain risk, cost risk, and reliability risk.

High-Current Trench Gate DMOSFET Incorporating Current Sensing FET for Motor Driver Applications

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.