Power Loop Inductance Research Articles

GaN-HEMT Power Module of Aluminum-Clad Printed Circuit Boards for Small Power Loop Inductance and High Cooling Performance

GaN-HEMT Power Module of Aluminum-Clad Printed Circuit Boards for Small Power Loop Inductance and High Cooling Performance

Design of Half-Bridge Switching Power Module Based on Parallel-Connected SiC MOSFETs for LLC Resonant Converter with Symmetrical Structure and Low Parasitic Inductance

SiC MOSFETs are used in many power conversion applications because of their superior characteristics, such as fast switching speed, low on-resistance, and high operating temperature. In certain high-power systems, SiC MOSFETs are connected in parallel to enhance their current capacity and power efficiency. However, compared with Si-based devices, the current imbalance caused by the parasitic inductance difference becomes more severe when driving SiC MOSFETs in parallel, owing to the fast switching speed. Furthermore, the power loop inductance imbalance that occurs when constructing a half-bridge with parallel SiC MOSFETs has rarely been addressed in previous studies. In this study, a half-bridge switching power module based on parallel-connected SiC MOSFETs is proposed to solve the current imbalance through a symmetric structure of the gate and power loops. The effects of the magnitude and imbalance of the gate and power loop inductances in the half-bridge structure based on parallel-connected devices are also explained. A detailed printed circuit board layout of the proposed switching power module is provided, and the inductance symmetry is verified through simulations. A double-pulse test is conducted to verify the current-balancing capability of the proposed switching power module. In addition, an LLC resonant converter is designed using the proposed switching power module, and the power loss between parallel SiC MOSFETs is compared. The experimental results indicate the total power loss error between the parallel-connected SiC MOSFETs of the proposed power module is only 1.94%.

Gate Voltage Oscillation Model and Suppression Method for Enhancement‐Mode GaN Devices in Half‐Bridge Circuits

This article analyzes the issue of gate voltage oscillations in AlGaN/GaN high electron mobility transistors based on the half‐bridge circuit. With the influence of the parasitic parameters, the variation of high drain‐source voltage (Vds) can affect the gate‐source voltage (Vgs), thus resulting in serious gate voltage oscillations, which may cause over‐voltage, false turn‐on/off, and even gate breakdown. A large‐signal model is proposed to study this oscillations phenomenon. The oscillation model of Vgs is proposed as a step response of Vds. Based on the model, the influence of Vds and circuit parameters on Vgs are investigated, and guidelines to suppress the oscillation are given. Reducing the gate and power loop inductance in PCB wiring and increasing the gate resistance of inactive switch can significantly suppress the oscillation. Finally, the model is verified by both simulation results and experimental results.

A High Power Density Double-Side-End Double-Sided Bonding SiC Half-Bridge Power Module

Silicon Carbide (SiC) power module with lower loop inductance, better dynamic current sharing properties and better thermal performance will contribute to achieve high power density three phase inverter in medium voltage applications. Inspired by the concept of double-side-end busbar, a novel double-side-end double sided bonding power module is proposed in this paper. For three chips parallel situation, double-side-end structure decreases parasitic inductance by 40% compared to that of traditional baseline structure. Besides lower parasitic inductance, novel structure also has better dynamic current sharing properties. To explain these dynamic current sharing phenomena, an equivalent source inductance model considering mutual inductance is proposed in this paper. A 1200V 10mΩ SiC double-side-end double sided bonding half-bridge power module is designed, fabricated and tested. Proposed power module realizes 3nH power loop inductance. Furthermore, to realize practical application of the novel power module, a novel compact two-level three-phase integration architecture based on novel power module is also proposed. With the help of the double-sided direct-cooling method and double-side-end busbar, proposed architecture will help to realize better performance.

A Reconfigurable AC Power Cycling Test Setup for Comprehensive Reliability Evaluation of GaN HEMTs

To address the challenges in long-term reliability testing of GaN power devices, this paper proposes a reconfigurable AC power cycling test setup. While addressing the limitations of existing aging tests, the proposed setup enables accelerated aging of GaN devices under a wide range of realistic stress conditions. Specifically, various hard and soft switching modes can be tested to realistically emulate different application scenarios. In addition to the ability to control test temperature, the setup also features adjustable power loop inductance that enables precise control over voltage overshoot during hard switching transients. Further, an on-state resistance based junction temperature estimation technique is used for closed loop junction temperature control. For this, a fast drain-source voltage measurement circuit along with an algorithm for closed-loop control of the mean junction temperature is presented in detail. Furthermore, the magnitudes of the temperature swing under different operation conditions are discussed in depth which provides a good insight to control temperature swings. Finally, a prototype is built to validate the proposed test design.

Low Parasitic-Inductance Packaging of a 650 V/150 A Half-Bridge Module Using Enhancement-Mode Gallium-Nitride High Electron Mobility Transistors

Because of their fast-switching speed and small die size, gallium-nitride high electron mobility transistors are challenging to package for low parasitic inductance and high heat dissipation in power electronics applications. In this article, a packaging technique was developed for making half-bridge modules of a 650 V, 150 A enhancement-mode gallium-nitride power transistor. The package consists of the device chips interconnected between a printed circuit board and an aluminum-nitride direct-bonded copper substrate. The dice are bonded on the insulated ceramic substrate by silver-sintering to ensure high thermal performance and joint reliability. The source, drain, and gate pads are connected by silver-sintering gold-plated pins or silver rods, which are aligned by holes or grooves in the circuit board. For electrical insulation and mechanical robustness, the space surrounding the device is filled by injecting and curing an underfill polymer. Electrical and thermal simulations of the package show that the half-bridge module has a 1.122 nH power-loop inductance, and 0.099 °C/W junction-to-case thermal resistance. Packages of the half-bridge module were fabricated, and their static and dynamic performances were characterized.

Design and Optimization of Gate Driver Integrated Multichip 3-D GaN Power Module

Gallium nitride (GaN) high electron mobility transistors (HEMTs) are excellent power semiconductor devices due to their superior material properties compared to their silicon (Si) counterparts. It has demonstrated a fast switching speed with high dV/dt, enabling the designer to push the switching frequency toward the MHz range. However, traditional wire-bonded packaging becomes a limiting factor in fully harnessing the benefits offered by these advanced power devices, as it is likely to introduce voltage overshoot, oscillation, parasitic turn-on, and electromagnetic interference (EMI) issues; thus, improved and advanced packaging structures are a must to bridge the gap. Besides, the unique electrical behavior and footprint of GaN compared to Si and Si carbide make them have different requirements for power module integration. To seek a viable solution, a globally optimized double-sided cooled, gate driver integrated 650-V/60-A GaN half-bridge power module is presented herein. The proposed 3-D integrated hybrid solution delivers an optimized package, having power loop inductance and thermal resistance as low as 0.91 nH and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.38~^{\circ }\text{C}$ </tex-math></inline-formula> /W, respectively, which is verified using simulation and experimental results. The overall utility of the design improved proportionately by introducing simple, yet effective electrical/thermal codesign approaches, which can be applied to future power modules, designed for separate applications.

Packaging of a 10-kV Double-Side Cooled Silicon Carbide Diode Module With Thin Substrates Coated by a Nonlinear Resistive Polymer-Nanoparticle Composite

Medium-voltage silicon carbide (SiC) power modules are a critical component in grid-bound power conversion systems, and the packaging of these modules dictates the performance and reliability of the systems. One of the key issues for packaging the modules is managing the tradeoff between heat dissipation and insulation. To improve thermal performance without sacrificing insulation, a 10-kV SiC full-wave diode rectifier was designed and fabricated by incorporating double-sided cooling and wirebond-less interconnection and by utilizing thin alumina direct-bond copper substrates. To ensure that the substrates met insulation requirement, triple points on the substrates were coated by a nonlinear resistive polymer-nanoparticle composite to reduce electric field concentration. The nonlinear resistive coating increased the partial discharge inception voltage of the substrate with 0.5-mm thick alumina to 17.3 kV, an 84% improvement over that of the substrate without the coating. Electrical and thermal simulations of the module showed a low power loop inductance of 3.51 nH and a low junction-to-case thermal resistance of 0.114°C/W. The feasibility of the packaging techniques was demonstrated from successful fabrication and functional testing of the packagedmodule.

Si-IGBT and SiC-MOSFET hybrid switch-based 1.7 kV half-bridge power module

• Design guidelines, fabrication process, and evaluation of a 1.7-kV and 300-A multi-chip half bridge power module using the novel Si-IGBT and SiC-MOSFET hybrid switch in each switch position. • The module achieves its maximum DC current rating with a 6:1 current ratio of Si to SiC. • A novel custom-designed TPG-encapsulated metal base plate is proposed. • Silver clips for top-side interconnect in the module, facilitating a wire bond-less interconnection, high reliability, and low power loop inductance. • High thermal dissipation capability while maintaining a near-isolated thermal path for the SiC MOSFET to operate at a higher temperature than the Si-IGBT. This paper informs the design guidelines, fabrication process, and evaluation of a 1.7-kV and 300-A multi-chip half bridge power module using the novel Si-IGBT and SiC-MOSFET hybrid switch in each switch position. The module achieves its maximum DC current rating with a 6:1 current ratio of Si to SiC. This high current ratio yields significant cost savings compared to an all-SiC power module. The module employs high-reliability silver clips, which replaces conventional wire bonds for top-side interconnection, to partly enable a low power loop inductance of 12.38 nH. A novel thermal pyrolytic graphite-encapsulated metal baseplate is key to reducing the thermal coupling among the adjacent Si and SiC die, enabling higher junction temperature for SiC die relative to the Si die.

A PCB-Embedded 1.2 kV SiC MOSFET Half-Bridge Package for a 22 kW AC–DC Converter

This article presents the design and analysis of a double-side-cooled printed circuit board (PCB) embedded silicon carbide (SiC) MOSFET half-bridge package with low loop inductances and an integrated gate driver. The 1.2 kV SiC MOSFET dies used in the half-bridge package are embedded in the PCB using AT&S's patented technique. The dies are cooled and electrically connected to traces in the PCB through copper-filled microvias. The design methodology accounts for both electrical and thermal performance, limiting the power-loop inductance to 2.3 nH and the maximum package temperature to less than the 175 °C limit. The integration of the gate drive circuitry allows for a high power density and 2.2 nH gate-loop inductances. At 0.12 K/W, the measured junction-to-case thermal resistance with double-sided cooling is 57% lower than that of a TO-247 package. Under similar operating conditions, the PCB-embedded half-bridge package also achieves a 5.6 times lower voltage overshoot and a 0.5% higher peak efficiency than a TO-247-based half-bridge. This article reports the first demonstration of PCB-embedded 1.2 kV SiC MOSFET packages in buck, boost, and ac–dc converters. The prototype three-phase ac–dc converter for an electric vehicle on-board charger is composed of six PCB-embedded half-bridge packages and achieves an efficiency of 98.2% and a power density of 182 W/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> .

Design Procedure and Efficiency Analysis of a 99.3% Efficient 10 kW Three-Phase Three-Level Hybrid GaN/Si Active Neutral Point Clamped Converter

High-efficient and power-dense ac–dc power electronic converters are demanded for a wide range of applications, such as motor drives and active rectifiers. The utilization of wide bandgap devices, such as gallium-nitride (GaN) transistors, is a key feature to improve both the efficiency and the power density of power electronic converters. Owing to the superiority of GaN switches, this article achieves a high-efficiency three-level active-neutral-point-clamped converter. However, using GaN transistors is critically dependent on the layout configuration to achieve smooth switching transient and, as equally important, efficient cooling. Therefore, this article presents layout optimization and considers different layout configurations to achieve a low power loop inductance and as efficient heatsink assembly/performance. Two configurations of the switch boards are built by GaN/Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s, and a power loop inductance comparison is presented. Furthermore, a comprehensive loss model is performed to fine-tune the switching frequency from the efficiency and the size point of view. A 10 kW laboratory prototype voltage source converter, including an electromagnetic interference (EMI) filter, is built with the switching frequency of 140 kHz. The efficiency measurement is performed and confirmed the full load efficiency of 99% and peak efficiency of 99.34%. Moreover, the CISPR11 Class A conducted EMI standard is fulfilled.

RPEM: Design and Realization of Reconfigurable Power Electronic Modules

A series of novel externally reconfigurable power electronic modules (RPEMs) are invented to increase the flexibility of power modules and their application purposes. In this article, the concept of RPEMs, their switching arrangements, and power-module-based architectural design are demonstrated. An RPEM is then designed, analyzed through simulations, and compared with the conventional fixed-configuration power electronic modules. The sizes of the power modules and used power terminals are kept similar to avoid any differences in power loop inductance values solely due to various trace pad sizes. In addition, similar gate/source pads and signal pins are used for all of the designed power modules to have constant switching dynamics in all modules. The comparison results show that the internal parasitic inductance and performance are still comparable with the conventional modules despite having high configurability. The designed RPEM and a conventional full-bridge (FB) power module are fabricated and characterized. The experimental tests show that the difference between the overshoot voltages on both RPEM and FB power modules is less than 2%. Such flexibility without compromising the power module performance decreases the engineering time for designing different power modules for various power electronic converters; hence, the production speed can be improved while decreasing the overall module cost.

Prediction of overshoot and crosstalk of low‐voltage GaN HEMT using analytical model

Ultra-fast switching speed and low switching loss of the gallium nitride high electron mobility transistors enable the realisation of high power density converter with excellent conversion efficiency. However, the rapid switching transition leads to significant overshoot and crosstalk issues that can degrade the performance of the devices. To facilitate the evaluation of these effects on low-voltage gallium nitride devices, this paper develops an analytical model to predict overshoot and crosstalk during switching transitions accurately and efficiently. The model is constructed based on the detailed circuit deduction of various stages of the device's switching process. It also considers the voltage-dependent junction capacitances as well as the forward and the reverse transconductances. The simulated results obtained from the model are validated experimentally. With the model, the impacts of parasitic elements, especially the power loop inductance, on voltage/current overshoots and spurious voltage due to crosstalk can be easily evaluated, which provides valuable design guidelines for power conversion applications using low-voltage gallium nitride high electron mobility transistor.

A Highly Integrated PCB Embedded GaN Full-Bridge Module With Ultralow Parasitic Inductance

To fully take the high-frequency advantage of gallium nitride (GaN) devices, this article presents a face-up integrated power module based on the printed circuit board embedding technology to tackle the challenges caused by the conventional discrete solutions. The proposed GaN module highly integrates a GaN-bare-dies-based full bridge, driving circuits, and decoupling capacitors, in which the advanced bismaleimide-triazine material is used as the packaging material and the copper-filled laser microvias are used for low-parasitic-inductance and high-thermal-conductivity interconnection. Careful electro-thermal codesign and optimization of power loop is conducted to make the tradeoff between power loop inductance and thermal performance. The proposed full bridge power module achieves the lowest power loop inductance of about 0.305 nH in power modules with the same power level. The maximum thermal resistances from the embedded GaN bare dies to top and bottom surface are 3.39 and 0.42 °C/W, respectively. Benefitting from the ultralow power loop parasitic inductances, the switching speed of GaN devices reaches to 57.5 V/ns, while the voltage overshoot is not higher than 5.35% of the dc bus voltage. The superior performance of the proposed integrated GaN module makes it a promising application prospect in high frequency high power density converters.

Layout-Based Ultrafast Short-Circuit Protection Technique for Parallel-Connected GaN HEMTs

Gallium-nitrideenhancement-mode high-electron-mobility transistors (GaN HEMTs) help to achieve high-power-density converter circuits due to their superior efficiency, higher switching speed, and small package size. However, increased switching speed results in a sharp increase in short-circuit (SC) current under a shoot-through fault with respect to other type of devices. GaN HEMTs can withstand the SC current only for several hundred nanoseconds. Therefore, fast SC protection solutions are critical for protecting power circuits. In this article, the voltage induced by high slew rate of SC current on the high-frequency power loop inductance resulting from the printed circuit board (PCB) layout is sensed to implement an ultrafast short-circuit protection technique. The proposed technique does not increase circuit parasitics and provides flexibility in layout design that makes it suitable for parallel-connected GaN HEMTs, which requires symmetric layout design for equal current sharing. A multipulse test is conducted under 1.56-MHz switching frequency, 400-V dc- bus voltage, and 40-A load current by using parallel-connected GaN HEMTs in a half-bridge configuration to verify the robustness and reliability of the proposed protection technique. Experimental results show that the proposed protection technique can detect SC fault within 40 ns and fault is completely cleared with a soft turn-off in 250 ns.

Research of Power Loop Layout and Parasitic Inductance in GaN Transistor Implementation

Power loop is critical in the PCB layout consideration. Especially for high frequency GaN transistor applications, a low inductance power loop design is needed to guarantee the switching reliability and the operation efficiency. Finite element analysis is generally used in the power loop inductance quantification, which is time consuming and impractical for parameters sweep. In this article, a numerical equation for power loop inductance estimation is given based on the novel loop inductance model. The power loop inductance can be estimated in a fast approximation approach. Three different layout methods are compared in regard to power loop inductance and thermal performance. A modular buck converter prototype is designed to demonstrate the effectiveness of the given numerical equation for power loop inductance estimation. The pros and cons of each layout method in the practical applications are discussed.

Vertically Stacked, Flip-Chip Wide Bandgap MOSFET Co-Optimized for Reliability and Switching Performance

Silicon carbide (SiC) wide-bandgap semiconductors (WBGs) offer a significant improvement in high voltage and high-temperature stability; however, their associated packaging often can impede electrical performance and reliability. In this study, a new flip-chip package, implementing a vertically oriented metal oxide semiconductor field effect transistor (MOSFET) was investigated to achieve co-optimized thermomechanical reliability with low parasitic inductance. The architecture improves upon wire-bonded packages by allowing for top-side cooling and reduced power loop inductance. Herein, the design effects of solder material and diameter as well as pitch size and drain connector geometry on thermal cycling reliability of the device were investigated using finite-element methods. Additionally, thermal resistance in association with a parasitic inductance of varying drain connector architectures is compared while utilizing symmetry to facilitate manufacturability. By considering the complex effects of geometry and material, the optimal architecture was selected and fabricated. When comparing to a prior flip-chip design effort, this simulation-based design optimization was able to improve the solder fatigue life up to 11 times while reducing parasitic inductance by 30 times. Experimentally, the associated electrical performance of the novel device showed improved switching behavior in double-pulse testing of a half-bridge module, with nearly negligible overshoot voltage on switching, where an equivalent discrete package exhibited ~100% overshoot and ~24% inductance improvement at the module level.

A High-Performance Embedded SiC Power Module Based on a DBC-Stacked Hybrid Packaging Structure

Silicon carbide (SiC) devices have the advantage of high switching speed. However, the switching speed is limited by the high parasitic inductance which could cause high voltage overshoot, parasitic turn-on, oscillation, and electromagnetic interference (EMI) issues. Thus, the parasitic inductance of the SiC power module has to be reduced for better performance. This paper proposed an integrated half-bridge (HB) power module based on a direct bonding copper (DBC)-stacked hybrid packaging structure. This packaging structure utilizes two DBC substrates to stack together, which form a 3-D power commutation loop. The SiC chips are embedded on the top of the bottom DBC substrate to reduce the thermal resistance. Based on an optimized mutual inductance cancellation design, the proposed DBC-stacked hybrid packaging structure has only 1.8-nH commutation power loop inductance for a 1200-V, 120-A HB power module. Moreover, the geometrical parameters of the laminated power terminal have been analyzed and optimized for the symmetrical current sharing in the multichip paralleled power module. A compact 1200-V, 120-A full SiC HB power module with integrated decoupling capacitors has been fabricated and the dc-link capacitor board, gate drivers can be integrated on the power module compactly. Finally, the static and dynamic characteristics of the proposed module have been tested. The results of double pulse test (DPT) under zero external driver resistor indicate that the voltage overshoot of the proposed module is reduced by approximately 55% compared to the commercial power module, and the total switching energy is only 43% of the commercial module. Moreover, the loss of the 5.5-kW single-phase inverter based on the proposed module is reduced by 28.3% compared with the inverter based on the commercial module under 120-kHz switching frequency.

Flexible PCB-Based 3-D Integrated SiC Half-Bridge Power Module With Three-Sided Cooling Using Ultralow Inductive Hybrid Packaging Structure

Silicon carbide (SiC) devices are capable of high switching speeds and also enable high switching frequency in power electronic converters. However, this feature poses substantial challenges to packaging, especially limiting the loop inductance. The traditional wire-bonding packaged power module has large parasitic inductance, which will cause voltage overshoot, oscillation, parasitic turn-on, and EMI issues. In order to reduce the parasitic inductance, this paper proposes a flexible printed circuit board (FPCB) based full SiC half-bridge power module with a novel low inductive hybrid packaging structure and three-dimensional (3-D) integration method. This hybrid packaging structure has an ultrathin FPCB substrate stacked on a direct bonding copper (DBC) substrate, which forms a multilayer 3-D power loop. The SiC chips are soldered on the DBC substrate for good thermal dissipation through a cavity in the FPCB substrate. After power loop optimization, the power loop inductance of a 1200-V/120-A SiC power module is only 0.79 nH. The power module consists of three submodules, which are connected by the bendable FPCB substrate. The bendable power module enables maximum utilization of 3-D space. The gate drive, decoupling capacitors, and dc-link capacitors are also integrated and 3D-structured using rigid-flexible PCBs. Moreover, the cooling system is a high-efficiency three-sided cooling structure for the bendable power module. The simulation results show that the three-sided cooling structure reduces the heatsink volume by 50%. Applying this method, the converter can be designed as a system-in-package and a 3D-structured compact system. The power density of a 20-kW three-phase inverter will reach 19.3 kW/L based on this power module. In this paper, the 1200-V/120-A power module fabrication and assembly processes are given. Finally, the static and dynamic experimental comparisons are done for a commercial power module and the proposed power module. The experiment results show that the voltage overshoot of the proposed module reduces about 5.8 times and are consistent with the simulation results. Meanwhile, the proposed power module switching speed is 1.8 times faster than the commercial module under zero external gate resistors and the switching loss can reduce by about 60%.

Electrical Performance Advancement in SiC Power Module Package Design With Kelvin Drain Connection and Low Parasitic Inductance

Silicon carbide (SiC) power modules are promising for high-power applications because of the high breakdown voltage, high operation temperature, low ON-resistance, and fast switching speed. However, the large parasitic inductance in existing package designs results in compromised performance, i.e., long blanking time in the desaturation protection scheme and large overvoltage spikes during the switching transient. Consequently, the benefits of SiC devices are often not fully utilized in practical applications. This paper deals with these two issues and aims at improving the electrical performance of the existing SiC module package. Specifically, a package design with Kelvin drain-to-source connection is first proposed to minimize the blanking time. More than 99% reduction of blanking time is achieved experimentally compared to the conventional package design. Second, a low parasitic inductance package with double-side cooling is proposed to allow the fast switching speed of SiC devices without sacrificing the thermal performance. A power loop inductance of 1.63 nH is realized from Q3D simulation. Verified by the experiment, more than 60% reduction of power loop inductance is achieved in comparison to a previously designed baseline module. At 0- $\Omega $ external gate resistance, the turn-off voltage spike is less than 9% of the dc-link voltage under the rated load condition.