Vertically Stacked, Flip-Chip Wide Bandgap MOSFET Co-Optimized for Reliability and Switching Performance

Abstract

Silicon carbide (SiC) wide-bandgap semiconductors (WBGs) offer a significant improvement in high voltage and high-temperature stability; however, their associated packaging often can impede electrical performance and reliability. In this study, a new flip-chip package, implementing a vertically oriented metal oxide semiconductor field effect transistor (MOSFET) was investigated to achieve co-optimized thermomechanical reliability with low parasitic inductance. The architecture improves upon wire-bonded packages by allowing for top-side cooling and reduced power loop inductance. Herein, the design effects of solder material and diameter as well as pitch size and drain connector geometry on thermal cycling reliability of the device were investigated using finite-element methods. Additionally, thermal resistance in association with a parasitic inductance of varying drain connector architectures is compared while utilizing symmetry to facilitate manufacturability. By considering the complex effects of geometry and material, the optimal architecture was selected and fabricated. When comparing to a prior flip-chip design effort, this simulation-based design optimization was able to improve the solder fatigue life up to 11 times while reducing parasitic inductance by 30 times. Experimentally, the associated electrical performance of the novel device showed improved switching behavior in double-pulse testing of a half-bridge module, with nearly negligible overshoot voltage on switching, where an equivalent discrete package exhibited ~100% overshoot and ~24% inductance improvement at the module level.