Power-gated Circuits Research Articles

A Novel STT–SOT MTJ-Based Nonvolatile SRAM for Power Gating Applications

This article proposes novel nonvolatile (NV) static random access memory (SRAM) circuits based on spin transfer torque (STT) and spin orbit torque (SOT) operated magnetic tunnel junction (MTJ) device for energy-efficient power gating circuits. In which, two different designs of 9T-2MTJs and 10T-2MTJ-based NV SRAM circuits are proposed for low power, high noise margin, and faster switching speed with less area overhead. The proposed architecture uses a smaller number of transistor combinations to accommodate low-power operation with compact cell size when compared with available pieces of literature. Also, the combination of nMOS and pMOS transistors in the proposed architecture enhances the driving capability of the circuit for both low and high input operations. Here, the electrical characteristics of the proposed designs have been compared and contrasted with the available 11T-2MTJ and 7T-2D-2MTJ non volatile static random access memory (NVSRAM) and 6T SRAM circuits using a UMC-40 nm design kit and physics-based STT–SOT MTJ Verilog-A Model. The proposed 9T-2MTJ-based NVSRAM was found to be a better alternative and offers improved performance in terms of higher restore noise margin and lower power consumption than other circuits reported at this node. Moreover, the studied 10T-2MTJ exhibits an improved write and hold noise margin than the proposed/available 9T/7T-2D/11T-2MTJ circuits.

Impact of Thermal Effects on the Performance of the Power Gating Circuits Using NEMS, FinFETs, and NWFETs

In this article, the power gating (PG) technique is analyzed using nano-electro-mechanical switches (NEMS), FinFETs, and nanowire field-effect transistors (NWFETs). We have used detailed circuit level simulations using well-calibrated models to obtain the conditions for net energy saving with thermal effects. We demonstrate that for a benchmark 17-stage buffer chain circuit, the NEMS PG will be superior to sub-10-nm FinFETs and NWFETs-based gating when the T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> on</sub> / T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> off</sub> ratio is less than 0.1 at room temperature. The ratio increases as temperature increases. Circuit simulations show that the energy gain ( T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> off</sub> = 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> ) due to NEMS gating increases by 3.6 times with reference to NWFETs and 7.3 times as compared to FinFETs-based gating when the temperature increases from 30 °C to 80 °C. NWFETs require a longer breakeven cycle for PG to become more energy-efficient than FinFETs due to its better gate control over the channel.

Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits

Background:With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits.Objective:The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits.Methods:A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit.Results:The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively.Conclusion:The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

Design Techniques for Power-Gated Nanoscale Low Power Circuits

Background: With the shrinking device-sizes in the present day world, the leakage power of the devices has also been increased significantly. Several techniques have been proposed to minimize the leakage power. However, the techniques have certain limitations, such as noise, delay or area of the chip. We have also proposed a leakage minimization technique which also minimizes the noise in the circuit. Objective: In this paper, we propose noise minimization circuit techniques for the distributed sleep transistor network in power-gated Multi-threshold CMOS circuits. The objective is to minimize leakage power as well as the noise associated with digital power-gated circuits. Methods: The proposed technique has been verified through simulations using the Cadence virtuoso tool. The proposed technique has been applied to a 16-bit adder circuit in 45 nm MTCMOS technology. Results: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve 99%, 64.8% and 62.07% reduction in noise as compared to the All-ON, variable-width and variable gate-voltage techniques, respectively. The behavior of the circuit techniques has also been analyzed at higher temperatures. It has been shown through simulations that the proposed techniques effectively minimize noise at higher temperatures i.e. 75°C and 115°C. The proposed techniques also minimize leakage power and the on-time delay significantly. A layout of the section of the proposed circuit has also been drawn which occupies the chip area of 2.37 µm2. Conclusion: The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve a significant reduction in the noise as well as delay. In this paper, we propose leakage minimization techniques for the distributed sleep transistor network. The proposed techniques i.e. HVT-ST and the Hybrid-ST techniques achieve a significant reduction in noise as well as delay. The technique also reduces the leakage power significantly.

Low Power Magnetic Non-volatile Flip-Flops with Self-Time Logical Writing for High-End Processors

Presently, leakage in a complementary metal oxide semiconductor (CMOS) increases due to high static power dissipation during reading and writing operations. Spin transfer torque magnetic random access memory is seen as the most reassuring non-volatile memory structure to overcome the current problem of static power dissipation. In conventional techniques, magnetic flip-flop (MFF) consumes large power and static current dissipation due to conditional-based single circuitry, which can be optimized through introduction of MFF with the combination of low swing conditional capture edge-trigged flip-flop, self-time logical writing circuit, and coarse-grain-based power gating circuit. This method has been developed particularly for high-precision, high-speed, mixed-mode application-specific integrated circuits; the reduction in total power consumption, static current, and PDP shows the proposed technique that as highly suitable for low power applications in high-end processors, using nanoscale technology. In this research work, results have been validated by simulations and measurements using 180 nm CMOS technology, tested using 1.8 v supply voltage.

Low Dropout Based Noise Minimization of Active Mode Power Gated Circuit

Power gating technique reduces leakage power in the circuit. However, power gating leads to large voltage fluctuation on the power rail during power gating mode to active mode due to the package inductance in the Printed Circuit Board. This voltage fluctuation may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in active mode and noise is analyzed. The effect of different noise minimization approaches for reducing power supply noise is evaluated in power gating architecture. A new concept of noise minimization technique using Low Dropout Voltage regulator is proposed in this paper. The amount of charge in the internal nodes of the power gating circuit passes through the sleep transistors during the wake-up transition is controlled by the proposed noise minimization techniques. The Low Dropout Voltage Regulator is designed newly in such a way that can be used to reduce bounce noise by minimizing voltage fluctuation on the power rail of power gating circuit. Architectures have been developed in Synopsys Custom Designer tool at iPDK 90nm technology. Percentage saving of noise on the power supply is reduced up to 99%.

A New Power Gating Circuit Design Approach Using Double-Gate FDSOI

Power gating circuits are utilized to manage power consumption and thermal stress in microprocessors and other high-performance integrated circuits. Most of the power gating techniques utilize sleep transistors in different configurations to reduce the subthreshold leakage current, which is the primary source of the standby power. These sleep transistors, which are added between the supply lines and the circuits as header and footer switches, impose additional area, delay, power, and other overheads and complexities. This brief introduces the concept of combining the functionality of the sleep transistors with the logic devices by utilizing fully depleted silicon-on-insulator (FDSOI) device. This FDSOI transistor-based power gating circuit design approach will eliminate the requirement of employing a separate set of sleep transistors to place the circuit in the sleep or idle mode. This will reduce the overall complexity and overheads of integrated circuits and simplify power gating techniques. In addition, it improves the overall power efficiency and lower thermal effects. SOI devices are becoming critically important for various very-large-scale integration applications, because SOI devices provide higher performance and reliability, and options to design circuits with multiple-threshold voltages to ensure faster switching and lower power consumption. In the proposed circuit design approach, the flexibility to control the threshold voltage of a double-gate FDSOI device via back gate has been exploited to eliminate the need for using a separate set of sleep transistors. The presented sleep transistor design is verified via HSPICE simulation using the Leti-UTSOI model from CEA-Leti .

Reliable Power Gating With NBTI Aging Benefits

In this paper, we show that negative bias temperature instability (NBTI) aging of sleep transistors (STs), together with its detrimental effect for circuit performance and lifetime (LT), presents considerable benefits for power-gated circuits. Indeed, it reduces static power due to leakage current, and increases ST switch efficiency, making power gating more efficient and effective over time. The magnitude of these aging benefits depends on operating and environmental conditions. By means of HSPICE simulations, considering a 32-nm CMOS technology, we demonstrate that static power may reduce by more than 80% in 10 years of operation. Static power decrease over time due to NBTI aging is also proven experimentally, using a test chip manufactured with a 65-nm technology. We propose an ST design strategy for reliable power gating, in order to harvest the benefits offered by NBTI aging. It relies on the design of STs with a proper lower $V_{\textrm {th}}$ compared with the standard STs. This can be achieved by either redesigning the STs with the identified $V_{\textrm {th}}$ value or applying a proper forward body bias to the available power switching fabrics. Through the HSPICE simulations, we show LT extension up to $21.4\times $ and average static power reduction up to 16.3% compared with the standard ST design approach, without additional area overhead. Finally, we show LT extension and several performance-cost tradeoffs when a target maximum LT is considered.

Macromodels for Static Virtual Ground Voltage Estimation in Power-Gated Circuits

Static virtual ground voltage $(V_\mathrm{gnd})$ is an important parameter to be accurately and efficiently estimated for fine-grained power gating in logic circuits. Previous work results in a large error in $V_\mathrm{gnd}$ estimation due to conservative leakage models and inaccurate assumption of voltage conditions at the input of CMOS gates in power-gated circuits. To overcome these problems, we propose support vector machine (SVM)-based macromodels to estimate the leakage current of CMOS gates and thus achieve effective reduction in error in leakage model characterization. These models are then used in SVM classifier (SVC) and regressor to formulate an SVM regression-based $V_\mathrm{gnd}$ model. The SVC results in 3 $\times$ savings in data generation time compared with HSPICE simulation to develop the final $V_\mathrm{gnd}$ model. The proposed model results in < 1% error and 23 000 times the speedup than HSPICE for the largest benchmark circuit.

Wakeup scheduling and its buffered tree synthesis for power gating circuits

Power gating circuit suffers from large amount of rush current during wakeup, especially when all switch cells are turned on simultaneously. If each switch cell is turned on at a different time, rush current can be reduced. It is shown in this paper that rush current can be reduced even more if signal transition time (or signal slew) to each switch cell is adjusted. We define wakeup scheduling as to determine turn-on time and signal slew of each switch cell; the goal is to minimize wakeup delay while keeping rush current below the maximum value that is allowed. The determined turn-on time and signal slew are implemented using a buffered tree. The wakeup scheduling and buffered tree construction are integrated into a design flow. To adapt to process variation, we use adjustable delay buffers in the wakeup network. We also apply grid-based design flow and use Schmitt triggers to implement large designs. Experiments in an industrial 1.1V, 32-nm technology demonstrate that the wakeup delay is reduced by 12% on average of example circuits compared with turn-on scheduling.

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

Modeling and Sizing of Power-Gating Single-Rail MOS Current Mode Logic

Almost all power-gating circuits used in MOS current-mode circuits were realized with dual-rail schemes. In this paper, a power-gating scheme for single-rail MOS current mode logic (SRMCML) is presented. The modeling of the sleep transistor in power-gating circuits is constructed and analyzed. The optimization methods for sizing sleep transistors of power-gating circuits are addressed in terms of energy dissipations. The design methods of the power-gating SRMCML circuits are presented. The effectiveness of the proposed power-gating structure is verified by using HSPICE simulations with a SMIC 130nm technology. From the outcomes of simulations, the energy loss of the power-gating SRMCML circuits is smaller than corresponding static CMOS alternatives in high frequencies.

A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors

Power-efficient designs are essential for micro-power sensor systems. This paper presents a power-gating scheme for MCML (MOS Current Mode Logic) circuits with separable-sizing sleep transistors. In the proposed scheme, two high-threshold power-gating transistors are inserted between load transistors and outputs of the MCML circuits. The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit. Basic cells and a 1-bit full adder are used to verify the correctness of the proposed scheme. The power consuming comparisons between conventional MCML and proposed power-gating MCML circuits are carried out. The 1-bit MCML full adder based on the proposed scheme nearly saves 36% of energy dissipations with respect to no-power-gating MCML one, for a power-gating activity of 0.6. Moreover, the proposed power-gating MCML circuit also has a great advantage in power dissipations in high frequency regions compared with the power-gating static CMOS ones. The power consumption of the MCML 1-bit full adder based on the proposed scheme is 63.2%, 44.8%, and 36.97% compared with the powergating static CMOS one when the operating frequency is 1GHz, 1.5GHz, and 2GHz, respectively.

Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes – sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages.

Power-Gating Scheme and Modeling of Near-Threshold Adiabatic Flip-Flops

Technology scaling increases the density and performance of nanometer circuits, resulting in both large dynamic and leakage dissipations. This paper presents power-gating scheme, modeling, and o ptimization of adiabatic flip-flops operating on n ear-threshold regions to reduce both dynamic and leakage dissipations. The power-gated logic blocks are realized with c omplementary pass-transistor adiabatic logic with the dual threshold technique to reduce active leakage dissipations. The improved c omplementary pass-transistor adiabatic logic circuits are used as the two-phase power-gating switches to reduce the sleep leakage dissipations. The analytical model for power-gating adiabatic sequential circuits was constructed, and the energy overhead of the proposed power-gating scheme was analyzed in detail. Near-threshold computing for a power-gating adiabatic mode-10 counter was verified. The results show that the proposed power-gating technique is suitable for the adiabatic units operating on near-threshold region s . DOI : http://dx.doi.org/10.11591/telkomnika.v12i1.3378

A Power-Gating Scheme for MOS Current Mode Logic Circuits

MOS Current-Mode Logic (MCML) is widely used for high-speed circuits. However, the MCML circuits have large static power consumptions due to their constant operation currents. This paper presents a power-gating scheme for MCML circuits to reduce their static power dissipations in sleep mode. The PMOS transistors for linear load resistors of MCML circuits are used for power-gating switches. A power-gating control circuit consisting of NMOS and PMOS transistors is added for switching power-gating switches under the control of the sleep signal. The structure and operation of the proposed power-gating scheme are presented. In order to verify the correctness of the proposed power-gating scheme, several basic cells and a full-adder based on MCML circuits are realized. All the circuits are simulated with HSPICE at SMIC 130nm technology. The simulation results show that the power dissipations of the MCML circuits can be greatly reduced by shutting down their idle logic blocks. DOI: http://dx.doi.org/10.11591/telkomnika.v11i10.2877

Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability

In an integrated circuit (IC) adopting a power-gating (PG) technique, the virtual supply voltage (VVDD) is susceptible to: 1) negative-bias temperature instability (NBTI) degradation that weakens the PG device over time and 2) temporal temperature variation that affects active leakage current (thus total current) of the IC. The PG device is sized to guarantee a minimum VVDD level over the chip lifetime. Thus, the NBTI degradation and the worst-case total current at high-temperature must be considered for sizing the PG device. This leads to higher VVDD (thus active leakage power) than necessary in early chip lifetime and/or at low temperature, negatively impacting the gate-oxide reliability of transistors. To reduce active leakage power increase and improve the gate-oxide reliability due to these effects, we propose two techniques that adjust the strength of a PG device based on its usage and IC's temperature at runtime. We demonstrate the efficacy of these techniques with an experimental setup using a 32-nm technology model in the presence of within-die spatial process and temperature variations. On an average of 100 die samples, they can reduce dynamic and active leakage power by up to 3.7% and 10% in early chip lifetime. Finally, these techniques also reduce the oxide failure rate by up to 5% across process corners over a period of 7 years.

Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning

Power gating is able to counter subthreshold leakage in low-power nanometer technology circuits without sacrificing performance. But mode transitions in power-gated circuits are accompanied by large inrush/discharge currents causing inductive bounce noise on the power supply and ground rails. This issue has been addressed by gradually turning on the sleep transistor; but this introduces a fixed lower bound on the delay overhead irrespective of the duration of the sleep period, and takes no account of the effects of changes in the circuit internal nodes during wake-up on the ground bounce noise. We observed the behavior of internal nodes during the sleep-to-active mode transition and identified three distinct stages. This motivates a three-step turn-on scheme and an associated compact power-gating structure that limits the current flowing through the sleep transistor only while the gated block is metastable, but quickly boosts the power supply rail when there are no short-circuit current paths in the logic. This strongly suppresses power gating noise, and also reduces wake-up time. Simulation results of 16-bit arithmetic logic units in 65-nm CMOS technology show that the proposed technique offers the advantage of a wake-up time that scales with the discharged value (during sleep) of the virtual power rail.

Design Techniques for NBTI-Tolerant Power-Gating Architectures

While negative bias temperature instability (NBTI) effects on logic gates are of major concern for the reliability of digital circuits, they become even more critical when considering the components for which even minimal parametric variations impact the lifetime of the overall circuit. pMOS header transistors used in power-gated architectures are one relevant example of such components. For these types of devices, an NBTI-induced current capability degradation translates into a larger -drop effect on the virtual- rail, which unconditionally affects the performance and, thus, the reliability of all power-gated cells. In this brief, we address the problem of designing NBTI-tolerant power-gating architectures. We propose a set of efficient NBTI-aware circuit design solutions, including both static and dynamic strategies, that aim at improving the lifetime stability of power-gated circuits by means of oversizing, body biasing, and stress-probability reduction while minimizing the design overheads. Experimental results prove the effectiveness of such techniques when applied to a suite of benchmarks mapped onto a 45-nm industrial CMOS technology library. In particular, we prove that it is possible to achieve more than ten times of lifetime extension with respect to a traditional power-gating approach.

Design and Optimization of Power-Gated Circuits With Autonomous Data Retention

Power gating has been widely employed to reduce subthreshold leakage. Data retention elements (flip-flops and isolation circuits) are used to preserve circuit states during standby mode, if the states are needed again after wake-up. These elements must be controlled by an external power management unit, causing a network of control signals implemented with extra wires and buffers. A power-gated circuit with autonomous data retention (APG) is proposed to remove the overhead involved in control signals. Retention elements in APG derive their control by detecting rising potential of virtual ground rails when power gating starts, i.e., they control themselves without explicit control signals. Design of retention elements for APG is addressed to facilitate safe capturing of circuit states. Experiments with 65-nm technology demonstrate that, compared to standard power gating, total wirelength, and average wiring congestion are reduced by 8.6% and 4.1% on average, respectively, at a cost of 6.8% area increase. In order to fast charge virtual ground rails, a pMOS switch driven by a short pulse is employed to directly provide charges to virtual ground. This helps retention elements avoid short-circuit current while making transition to standby mode. The optimization procedure for sizing pMOS switch and deciding pulse width is addressed, and assessed with 65-nm technology. Experiments show that, compared to standard power gating, APG reduces the delay to enter and exit the standby mode by 65.6% and 28.9%, respectively, with corresponding energy dissipation during the period cut by 46.1% and 36.5%. Standby mode leakage power consumption is also reduced by 15.8% on average.